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DAC3151 View Datasheet(PDF) - Texas Instruments

Part NameDescriptionManufacturer
DAC3151 Single 14-/12-/10-Bit 500 MSPS Digital-to-Analog Converters TI
Texas Instruments TI
DAC3151 Datasheet PDF : 57 Pages
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DAC3151
DAC3161
DAC3171
SLAS959A – AUGUST 2013 – REVISED AUGUST 2013
Register name: config0 – Address: 0x00, Default: 0x4FC
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Register
Name
config0
Addr
(Hex)
Bit
0x00 15
14
Name
qmc_offset_ena
dual_ena
13:12 chipwidth
11
rev
10
twos
9
sif4_ena
8
reserved
7
fifo_ena
6
alarm_out_ena
5
alarm_out_pol
4
alignrx_ena
3
lvdssyncrx_ena
2
lvdsdataclk_ena
1
reserved
0
synconly_ena
Function
Default Value
Enable the offset function when asserted.
0
Utilizes both DACs when asserted.
0
FUSE
controlled
Programmable bits for setting the input interface width.
00
00: all 14 bits are used.
01: upper 12 bits are used10: upper 10 bits are used
11: upper 10 bits are used
Reverses the input bits. When using the 7bit interface, this 0
reverse each 7-bit input, however when using the 14-bit
interface, all 14-bits are reversed as one word.
When asserted, this bit tells the chip to presume 2’s
1
complement data is arriving at the input. Otherwise offset
binary is presumed.
When asserted the SIF interface becomes a 4 pin interface. 0
This bit has a lower priority than the dieid_ena bit.
reserved
0
When asserted, the FIFO is absorbing the difference between 1
INPUT clock and DAC clock. If it is not asserted then the
FIFO buffering is bypassed but the reversing of bits and
handling of offset binary input is still available. NOTE: When
the FIFO is bypassed the DACCCLK and DATACLK must
be aligned or there may be timing errors; and, it is not
recommended for actual application use.
When asserted the pin alarm becomes an output instead of a 1
tri-stated pin.
This bit changes the polarity of the ALARM signal.
1
(0=negative logic, 1=positive logic)
When asserted the ALIGN pin receiver is powered up. NOTE: 1
It is recommended to clear this bit when ALIGNP/N are
not used (dual bus mode, and SYNC ONLY and
SIF_SYNC modes in single bus mode).
When asserted the SYNC pin receiver is powered up. NOTE: 1
1 It is recommended to clear this bit when SYNCP/N are
not used (dual bus mode, and SIF_SYNC mode in single
bus mode.)
When asserted the DATACLK pin receiver is powered up.
1
reserved
0
When asserted the chip is put into the SYNC ONLY mode
0
where the SYNC pin is used as the sync input for both the
front and back of the FIFO.
38
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