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DAC34SH84 View Datasheet(PDF) - Texas Instruments

Part NameDescriptionManufacturer
DAC34SH84 Quad-Channel, 16-Bit, 1.5 GSPS Digital-to-Analog Converter (DAC) TI
Texas Instruments TI
DAC34SH84 Datasheet PDF : 77 Pages
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DAC34SH84
www.ti.com
SLAS808B – FEBRUARY 2012 – REVISED JULY 2012
5. Verify there are no FIFO alarms either through register config5 or through the ALARM pin.
6. Disable clock divider sync by setting clkdiv_sync_ena to 0 in register config0.
After these steps all the DAC34SH84 outputs will be synchronized.
MULTI-DEVICE OPERATION: SINGLE SYNC SOURCE MODE
In Single Sync Source mode, the FIFO write and read pointers are reset from the same sync source, either ISTR
or SYNC. Although the FIFO in this mode can still absorb the data delay differences due to variations in the
digital source output paths or board level wiring it is impossible to guarantee data will be read from the FIFO of
different devices simultaneously thus preventing exact phase alignment.
In Single Sync Source mode the FIFO read pointer reset is handoff between the two clock domains (DATACLK
and FIFO OUT CLOCK) by simply re-sampling the write pointer reset. Since the two clocks are asynchronous
there is a small but distinct possibility of a meta-stablility during the pointer handoff. This meta-stability can cause
the outputs of the multiple devices to slip by up to 2 DAC clock cycles.
When the PLL is enabled with Single Sync Source mode, the FIFO read pointer is not synchronized by the
OSTR signal. Therefore, there is no restriction on the PLL PFD frequency as described in the previous section.
DACCLKP/N
FPGA
LVPECL Outputs
Clock Generator
LVPECL Outputs
PLL/
DLL
DAB[15:0]P/N
DCD[15:0]P/N
ISTRP/N
Delay 1
DATACLKP/N
DAC34SH84 DAC1
Variable delays due to variations in the FPGA(s) output
DAB[15:0]P/N paths or board level wiring or temperature/voltage deltas
DCD[15:0]P/N
ISTRP/N
Delay 2
DATACLKP/N
DAC34SH84 DAC2
0 to 2 DAC Clock Cycles
DACCLKP/N
Figure 61. Multi-Device Operation in Single Sync Source Mode
B0456-04
FIR FILTERS
Figure 62 through Figure 65 show the magnitude spectrum response for the FIR0, FIR1, FIR2 and FIR3
interpolating filters where fIN is the input data rate to the FIR filter. Figure 66 to Figure 69 show the composite
filter response for 2x, 4x, 8x and 16x interpolation. The transition band for all interpolation settings is from 0.4 to
0.6 x fDATA (the input data rate to the device) with < 0.001dB of pass-band ripple and > 90 dB stop-band
attenuation.
The DAC34SH84 also has a 9-tap inverse sinc filter (FIR4) that runs at the DAC update rate (fDAC) that can be
used to flatten the frequency response of the sample-and-hold output. The DAC sample-and-hold output sets the
output current and holds it constant for one DAC clock cycle until the next sample, resulting in the well-known
sin(x) / x or sinc(x) frequency response (Figure 70, red line). The inverse sinc filter response (Figure 70, blue
line) has the opposite frequency response from 0 to 0.4 x Fdac, resulting in the combined response (Figure 70,
green line). Between 0 to 0.4 x fDAC, the inverse sinc filter compensates the sample-and-hold roll-off with less
than 0.03 dB error.
Copyright © 2012, Texas Instruments Incorporated
Product Folder Link(s): DAC34SH84
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