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DAC34SH84 View Datasheet(PDF) - Texas Instruments

Part NameDescriptionManufacturer
DAC34SH84 Quad-Channel, 16-Bit, 1.5 GSPS Digital-to-Analog Converter (DAC) TI
Texas Instruments TI
DAC34SH84 Datasheet PDF : 77 Pages
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DAC34SH84
SLAS808B – FEBRUARY 2012 – REVISED JULY 2012
www.ti.com
The following steps are required to ensure the devices are fully synchronized. The procedure assumes all the
DAC34SH84 devices have a DACCLK and OSTR signal and must be carried out on each device.
1. Start-up the device as described in the power-up sequence. Set the DAC34SH84 in Dual Sync Sources
mode and select OSTR as the clock divider sync source (clkdiv_sync_sel in register config32).
2. Sync the clock divider and FIFO pointers.
3. Verify there are no FIFO alarms either through register config5 or through the ALARM pin.
4. Disable clock divider sync by setting clkdiv_sync_ena to 0 in register config0.
After these steps all the DAC34SH84 outputs will be synchronized.
MULTI-DEVICE SYNCHRONIZATION: PLL ENABLED WITH DUAL SYNC SOURCES MODE
The DAC34SH84 allows exact phase alignment between multiple devices even when operating with the internal
PLL clock multiplier. In PLL clock mode, the PLL generates the DAC clock and an internal OSTR signal from the
reference clock applied to the DACCLK inputs so there is no need to supply an additional LVPECL OSTR signal.
For this method to operate properly the SYNC signal should be set to reset the PLL N dividers to a known state
by setting pll_ndivsync_ena in register config24 to 1. The SYNC signal resets the PLL N dividers with a rising
edge, and the timing relationship ts(SYNC_PLL) and th(SYNC_PLL) are relative to the reference clock presented on the
DACCLK pin.
Both SYNC and DACCLK can be set as low frequency signals to greatly simplifying trace routing (SYNC can be
just a pulse as a single rising edge is required, if using a periodic signal it is recommended to clear the
pll_ndivsync_ena bit after resetting the PLL dividers). Besides the ts(SYNC_PLL) and th(SYNC_PLL) requirement
between SYNC and DACCLK, there is no additional required timing relationship between the SYNC and ISTR
signals or between DACCLK and DATACLK. The only restriction as in the PLL disabled case is that the DACCLK
and SYNC signals are distributed from device to device with the lowest skew possible.
DACCLKP/N
Outputs
FPGA
SYNCP/N
DAB[15:0]P/N
DCD[15:0]P/N
ISTRP/N
Delay 1
DATACLKP/N
DAC34SH84 DAC1
Clock Generator
Outputs
PLL/
DLL
Variable delays due to variations in the FPGA(s) output
DAB[15:0]P/N paths or board level wiring or temperature/voltage deltas
DCD[15:0]P/N
ISTRP/N
Delay 2
DATACLKP/N
SYNCP/N
DAC34SH84 DAC2
Outputs are
Phase Aligned
DACCLKP/N
Figure 60. Synchronization System in Dual Sync Sources Mode With PLL Enabled
B0455-04
The following steps are required to ensure the devices are fully synchronized. The procedure assumes all the
DAC34SH84 devices have a DACCLK and OSTR signal and must be carried out on each device.
1. Start up the device as described in the power-up sequence. Set the DAC34SH84 in Dual Sync Sources
mode and enable SYNC to reset the PLL dividers (set pll_ndivsync_ena in register config24 to 1).
2. Reset the PLL dividers with a rising edge on SYNC.
3. Disable PLL dividers resetting.
4. Sync the clock divider and FIFO pointers.
50
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