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DAC34SH84 View Datasheet(PDF) - Texas Instruments

Part NameDescriptionManufacturer
DAC34SH84 Quad-Channel, 16-Bit, 1.5 GSPS Digital-to-Analog Converter (DAC) TI
Texas Instruments TI
DAC34SH84 Datasheet PDF : 77 Pages
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DAC34SH84
SLAS808B – FEBRUARY 2012 – REVISED JULY 2012
www.ti.com
NAME
AVDD
ALARM
PIN
NO.
D10, E11,
F11, G11,
H11, J11,
K11, L10
N12
BIASJ
H12
CLKVDD
C12, K12
DAB[15..0]P
DAB[15..0]N
DCD[15..0]P
DCD[15..0]N
DACCLKP
DACCLKN
DACVDD
A7, A6, A5,
A4, A3, A2,
A1, C4, C2,
D4, D2, E4,
E2, F4, F2,
G4
B7, B6, B5,
B4, B3, B2,
B1, C3, C1,
D3, D1, E3,
E1, F3, F1,
G3
H4, J4, J2,
K4, K2, L4,
L2, M4, M2,
N1, N2, N3,
N4, N5, N6,
N7
H3, J3, J1,
K3, K1, L3,
L1, M3, M1,
P1, P2, P3,
P4, P5, P6,
P7
A12
A11
D9, E9, E10,
F10, G10,
H10, J10,
K10, K9, L9
DATACLKP G2
DATACLKN
DIGVDD
G1
E5, E6, E7,
F5, J5, K5,
K6, K7
EXTIO
G12
ISTRP/
PARITYABP
H2
ISTRN/
PARITYABN
H1
PIN FUNCTIONS
I/O
DESCRIPTION
I Analog supply voltage. (3.3 V)
CMOS output for ALARM condition. The ALARM output functionality is defined through the config7
O register. Default polarity is active-high, but can be changed to active-low via the config0
alarm_out_pol control bit.
O
Full-scale output current bias. For 30-mA full-scale output current, connect 1.28 kΩ to ground.
Change the full-scale output current through coarse_dac(3:0) in config3, bit<15:12>.
I
Internal clock buffer supply voltage. (1.35 V). It is recommended to isolate this supply from DIGVDD
and DACVDD.
LVDS positive input data bits 0 through 15 for the AB-channel path. Internal 100-termination
resistor. Data format relative to DATACLKP/N clock is double data rate (DDR).
I
DAB15P is the most-significant data bit (MSB).
DAB0P is the least-significant data bit (LSB).
The order of the bus can be reversed via the config2 revbus bit.
I
LVDS negative input data bits 0 through 15 for the AB-channel path. (See the preceding DAB[15:0]P
description.)
LVDS positive input data bits 0 through 15 for the CD-channel path. Internal 100-termination
resistor. Data format relative to DATACLKP/N clock is double data rate (DDR).
I
DCD15P is the most-significant data bit (MSB).
DCD0P is the least-significant data bit (LSB).
The order of the bus can be reversed via the config2 revbus bit.
I
LVDS negative input data bits 0 through 15 for the CD-channel path. (See the preceding DCD[15:0]P
description.)
I Positive external LVPECL clock input for DAC core with a self-bias
I Complementary external LVPECL clock input for DAC core. (See the DACCLKP description.)
I
DAC core supply voltage. (1.35 V). It is recommended to isolate this supply from CLKVDD and
DIGVDD.
I
LVDS positive input data clock. Internal 100-termination resistor. Input data DAB[15:0]P/N and
DCD[15:0]P/N are latched on both edges of DATACLKP/N (double data rate).
I LVDS negative input data clock. (See the DATACLKP description.)
I Digital supply voltage. (1.3 V). It is recommended to isolate this supply from CLKVDD and DACVDD.
Used as an external reference input when the internal reference is disabled through config27
I/O extref_ena = 1. Used as an internal reference output when config27 extref_ena = 0 (default).
Requires a 0.1-μF decoupling capacitor to AGND when used as a reference output.
LVDS input strobe positive input. Internal 100-termination resistor
The main functions of this input are to sync the FIFO pointer, to provide a sync source to the digital
blocks, and/or to act as a parity input for the AB-data bus.
I These functions are captured with the rising edge of DATACLKP/N. This signal should be edge-
aligned with DAB[15:0]P/N and DCD[15:0]P/N.
The PARITY, SYNC, and ISTR inputs are rotated to allow complete reversal of the data interface
when setting the rev_interface bit in register config1.
I LVDS input strope negative input. (See the ISTRP/PARITYABP description.)
4
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