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DAC34SH84 View Datasheet(PDF) - Texas Instruments

Part NameDescriptionManufacturer
DAC34SH84 Quad-Channel, 16-Bit, 1.5 GSPS Digital-to-Analog Converter (DAC) TI
Texas Instruments TI
DAC34SH84 Datasheet PDF : 77 Pages
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The N divider in the loop allows the PFD to operate at a lower frequency than the reference clock. Both M and N
dividers can keep the PFD frequency below 155 MHz for peak operation.
The overall divide ratio inside the loop is the product of the pre-scale and M dividers (P × M), and the following
guidelines should be followed:
• The overall divide ratio range is from 24 to 480.
• When the overall divide ratio is less than 120, the internal loop filter can assure a stable loop.
• When the overall divide ratio is greater than 120, an external loop filter or double charge pump is required to
ensure loop stability.
The single- and double-charge-pump current options are selected by setting pll_cp in register config24 to 01 and
11, respectively. When using the double-charge-pump setting, an external loop filter is not required. If an external
loop filter is required, the following filter should be connected to the LPF pin (A1):
R = 1 kΩ
C1 = 100 nF
C2 = 1 nF
Figure 57. Recommended External Loop Filter
The PLL generates an internal OSTR signal and does not require the external LVPECL OSTR signal. The OSTR
signal is buffered from the N-divider output in the PLL block, and the frequency of the signal is the same as the
PFD frequency. Therefore, using the PLL with dual-sync-sources mode would require the PFD frequency to be
the pre-defined OSTR frequency. This allows the FIFO to be synced correctly by the internal OSTR.
In various applications, such as multi antenna systems where the various transmit channels information is
correlated, it is required that multiple DAC devices are completely synchronized such that their outputs are phase
aligned. The DAC34SH84 architecture supports this mode of operation.
For single- or multi-device synchronization it is important that delay differences in the data are absorbed by the
device so that latency through the device remains the same. Furthermore, to ensure that the outputs from each
DAC are phase aligned it is necessary that data is read from the FIFO of each device simultaneously. In the
DAC34SH84 this is accomplished by operating the multiple devices in Dual Sync Sources mode. In this mode
the additional OSTR signal is required by each DAC34SH84 to be synchronized.
Data into the device is input as LVDS signals from one or multiple baseband ASICs or FPGAs. Data into multiple
DAC devices can experience different delays due to variations in the digital source output paths or board level
wiring. These different delays can be effectively absorbed by the DAC34SH84 FIFO so that all outputs are phase
aligned correctly.
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