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DAC34SH84 View Datasheet(PDF) - Texas Instruments

Part NameDescriptionManufacturer
DAC34SH84 Quad-Channel, 16-Bit, 1.5 GSPS Digital-to-Analog Converter (DAC) TI
Texas Instruments TI
DAC34SH84 Datasheet PDF : 77 Pages
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DAC34SH84
www.ti.com
SLAS808B – FEBRUARY 2012 – REVISED JULY 2012
The DAC34SH84 PLL mode is selected by setting the following:
1. pll_ena bit in register config24 to 1 to route to the PLL clock path.
2. pll_sleep bit in register config26 to 0 to enable the PLL and VCO.
The output frequency of the VCO is designed to be the in the range from 2.7 GHz to 3.3 GHz. The prescaler
value, pll_p(2:0) in register config24, should be chosen such that the product of the prescaler value and DAC
sample rate clock is within the VCO range. To maintain optimal PLL loop, the coarse-tuning bits, pll_vco(5:0) in
register config26, can adjust the center frequency of the VCO toward the product of the prescaler value and DAC
sample-rate clock. Figure 56 shows a typical relationship between the coarse-tuning bits and VCO center
frequency.
3300
3200
VCO Frequency (MHz) - 2673
Coarse-Tuning Bits @
9.7
3100
3000
2900
2800
2700
0
8
16
24
32
40
48
56
64
Coarse-Tuning Bits
Figure 56. Typical PLL/VCO Lock Range vs Coarse-Tuning Bits
Common wireless infrastructure frequencies (614.4MHz, 737.28MHz, 983.04 MHz, and so forth) are generated
from this VCO frequency in conjunction with the prescaler setting as shown in Table 5.
VCO Frequency (MHz)
2949.12
3072
2949.12
2949.12
2949.12
Table 5. VCO Operation
Pre-Scale Divider
6
5
4
3
2
Desired DACCLK (MHz)
491.52
614.4
737.28
983.04
1474.56
pll_p(2:0)
110
101
100
011
010
The M divider is used to determine the phase-frequency-detector (PFD) and charge-pump (CP) frequency.
DACCLK Frequency
(MHz)
491.52
491.52
491.52
491.52
Table 6. PFD and CP Operation
M Divider
4
8
16
32
PFD Update Rate (MHz)
122.88
61.44
30.72
15.36
pll_m(7:0)
0000 0100
0000 1000
0001 0000
0010 0000
Copyright © 2012, Texas Instruments Incorporated
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