SLAS808B – FEBRUARY 2012 – REVISED JULY 2012
In those applications requiring extremely low noise it is recommended to bypass the PLL and source the DAC
clock directly from a high-quality external clock to the DACCLK input. In most applications, system clocking can
be simplified by using the on-chip PLL to generate the DAC core clock while still satisfying performance
requirements. In this case, the DACCLK pins are used as the reference frequency input to the PLL.
Figure 54. Top-Level Clock Diagram
PLL BYPASS MODE
In PLL bypass mode, a very high-quality clock is sourced to the DACCLK inputs. This clock is used to directly
source the DAC34SH84 DAC sample-rate clock. This mode gives the device best performance and is
recommended for extremely demanding applications.
The bypass mode is selected by setting the following:
1. pll_ena bit in register config24 to 0 to bypass the PLL circuitry.
2. pll_sleep bit in register config26 to 1 to put the PLL and VCO into sleep mode.
In this mode, the clock at the DACCLKP/N input functions as a reference clock source to the on-chip PLL. The
on-chip PLL then multiplies this reference clock to supply a higher-frequency DAC sample-rate clock. Figure 55
shows the block diagram of the PLL circuit.
OSTR (Internally Generated)
The PLL generates internal OSTR signal. In this mode
external LVPECL OSTR signal is not required.
If the DAC is configured with PLL enabled with Dual Sync
Sources mode, then the PFD frequency has to be the pre-
defined OSTR frequency.
Figure 55. PLL Block Diagram
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