datasheetbank_Logo     Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site

DAC34SH84 View Datasheet(PDF) - Texas Instruments

Part NameDescriptionManufacturer
DAC34SH84 Quad-Channel, 16-Bit, 1.5 GSPS Digital-to-Analog Converter (DAC) TI
Texas Instruments TI
DAC34SH84 Datasheet PDF : 77 Pages
First Prev 41 42 43 44 45 46 47 48 49 50 Next Last
DAC34SH84
SLAS808B – FEBRUARY 2012 – REVISED JULY 2012
www.ti.com
Similarly, the read pointer sync source is selected by syncsel_fifoout(3:0). The write pointer sync source can be
set to reset the read pointer as well. In this case, the FIFO-out clock recaptures the write pointer sync signal to
reset the read pointer. This clock domain transfer (DATACLK to FIFO Out Clock) results in phase ambiguity of
the sync signal. This limits the precise control of the output timing and makes full synchronization of multiple
devices difficult.
To alleviate this, the device offers the alternative of resetting the FIFO read pointer independently of the write
pointer by using the OSTR signal. The OSTR signal is sampled by DACCLK and must satisfy the timing
requirements in the specifications table. In order to minimize the skew it is recommended to use the same clock
distribution device such as Texas Instruments CDCE62005 to provide the DACCLK and OSTR signals to all the
DAC34SH84 devices in the system. Swapping the polarity of the DACCLK outputs with respect to the OSTR
ones establishes proper phase relationship.
The FIFO pointers reset procedure can be done periodically or only once during initialization as the pointers
automatically return to the initial position when the FIFO has been filled. To reset the FIFO periodically, it is
necessary to have the ISTR, SYNC, and OSTR signals to repeat at multiples of 8 FIFO samples. To disable
FIFO reset, set syncsel_fifoin(3:0) and syncsel_fifoout(3:0) to 0000.
The frequency limitation for ISTR and SYNC signals are the following:
fsync = fDATACLK / (n × 8), where n = 1, 2, …
The frequency limitation for the OSTR signal is the following:
fOSTR = fDAC / (n × interpolation × 8) where n = 1, 2, …
The frequencies above are at maximum when n = 1. This is when the ISTR, SYNC, or OSTR have a rising edge
transition every 8 FIFO samples. The occurrence can be made less frequent by setting n > 1, for example, every
n × 8 FIFO samples.
D[15:0]P/N
DATACLKP/N
(DDR)
ISTRP/N
SYNCP/N
tS(DATA)
tS(DATA)
tH(DATA)
tH(DATA)
Resets Write Pointer to Position 0
tS(DATA)
tH(DATA)
DACCLKP/N
2x Interpolation
OSTRP/N
(optionally internal
sync from Write Reset)
tS(OSTR)
tH(OSTR)
Resets Read Pointer to Position
Set by fifo_offset (4 by Default)
Figure 53. FIFO Write and Read Descriptions
T0531-01
FIFO MODES OF OPERATION
The DAC34SH84 input FIFO can be completely bypassed through registers config0 and config32. The register
configuration for each mode is described in Table 4.
44
Submit Documentation Feedback
Product Folder Link(s): DAC34SH84
Copyright © 2012, Texas Instruments Incorporated
Direct download click here

 

Share Link : 

All Rights Reserved © datasheetbank.com 2014 - 2019 [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]