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DAC34SH84 View Datasheet(PDF) - Texas Instruments

Part NameDescriptionManufacturer
DAC34SH84 Quad-Channel, 16-Bit, 1.5 GSPS Digital-to-Analog Converter (DAC) TI
Texas Instruments TI
DAC34SH84 Datasheet PDF : 77 Pages
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DAC34SH84
www.ti.com
SLAS808B – FEBRUARY 2012 – REVISED JULY 2012
INPUT FIFO
The DAC34SH84 includes a 4-channel, 16-bit-wide and 8-sample-deep input FIFO which acts as an elastic
buffer. The purpose of the FIFO is to absorb any timing variations between the input data and the internal DAC
data-rate clock, such as the ones resulting from clock-to-data variations from the data source.
Figure 52 shows a simplified block diagram of the FIFO.
Clock Handoff
DAB[15:0]
DCD[15:0]
ISTR/
SYNC
Input Side
Clocked by DATACLK
16-Bit
A-Data, 16-Bit
16-Bit
16-Bit
De-Interleave
B-Data, 16-Bit
C-Data, 16-Bit
D-Data, 16-Bit
16-Bit
Write Pointer Reset
FIFO:
4 x 16-Bits Wide
8-Samples deep
Output Side
Clocked by FIFO Out Clock
(DACCLK/Interpolation Factor)
Initial
Position
Sample 0
0 A0[15:0], B0[15:0], C0[15:0], D0[15:0] 0
64-Bit
Sample 0
1 A1[15:0], B1[15:0], C1[15:0], D1[15:0] 1
Sample 0
2 A2[15:0], B2[15:0], C2[15:0], D2[15:0] 2
64-Bit
Sample 0
3 A3[15:0], B3[15:0], C3[15:0], D3[15:0] 3 Initial
Sample 0
Position
4 A4[15:0], B4[15:0], C4[15:0], D4[15:0] 4
Sample 0
5 A5[15:0], B5[15:0], C5[15:0], D5[15:0] 5
Sample 0
6 A6[15:0], B6[15:0], C6[15:0], D6[15:0] 6
Sample 0
7 A7[15:0], B7[15:0], C7[15:0], D7[15:0] 7
16-Bit
16-Bit
16-Bit
16-Bit
FIFO A Output
FIFO B Output
FIFO C Output
FIFO D Output
Read Pointer Reset
FIFO Reset
fifo_offset(2:0)
SM
syncsel_fifoout
OSTR
syncsel_fifoin
S (Single Sync Sources Mode): Reset handoff from
input side to output side
M (Dual Sync Source Mode): OSTR resets read
pointer. Allows Multi-DAC synchronization
Figure 52. DAC34SH84 FIFO Block Diagram
B0461-01
Data is written to the device 32 bits at a time on the rising and falling edges of DATACLK. In order to form a
complete 64-bit wide sample (16-bit A-data, 16-bit B-data, 16-bit C-data, and 16-bit D-data) one DATACLK
period is required. Each 64-bit-wide sample is written into the FIFO at the address indicated by the write pointer.
Similarly, data from the FIFO is read by the FIFO-out clock 64 bits at a time from the address indicated by the
read pointer. The FIFO-out clock is generated internally from the DACCLK signal and its rate is equal to
DACCLK / interpolation. Each time a FIFO write or FIFO read is done, the corresponding pointer moves to the
next address.
The reset position for the FIFO read and write pointers is set by default to addresses 0 and 4 as shown in
Figure 52. This offset gives optimal margin within the FIFO. The default read pointer location can be set to
another value using fifo_offset(2:0) in register config9 (address 4 by default). Under normal conditions, data is
written to and read from the FIFO at the same rate and consequently, the write and read pointer gap remains
constant. If the FIFO write and read rates are different, the corresponding pointers cycle at different speeds,
which could result in pointer collision. Under this condition, the FIFO attempts to read and write data from the
same address at the same time, which results in errors and thus must be avoided.
The write pointer sync source is selected by syncsel_fifoin(3:0) in register config32. In most applications either
ISTR or SYNC are used to reset the write pointer. Unlike DATA, the sync signal is latched only on the rising
edges of DATACLK. A rising edge on the sync signal source causes the pointer to return to its original position.
Copyright © 2012, Texas Instruments Incorporated
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