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DAC34SH84 View Datasheet(PDF) - Texas Instruments

Part NameDescriptionManufacturer
DAC34SH84 Quad-Channel, 16-Bit, 1.5 GSPS Digital-to-Analog Converter (DAC) TI
Texas Instruments TI
DAC34SH84 Datasheet PDF : 77 Pages
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DAC34SH84
SLAS808B – FEBRUARY 2012 – REVISED JULY 2012
www.ti.com
DATA INTERFACE
The DAC34SH84 has a 32-bit LVDS bus that accepts quad, 16-bit data in word-wide format. The quad, 16-bit
data can be input to the device using a dual-bus, 16-bit interface. The bus accepts LVDS transfer rates up to 1.5
GSPS, which corresponds to a maximum data rate of 750 MSPS per data channel. The default LVDS bus input
assignment is shown in Table 3.
Table 3. LVDS Bus Input Assignment
Data Paths
A and B
C and D
Pins
DAB[15..0]
DCD[15..0]
Data is sampled by the LVDS double-data-rate (DDR) clock DATACLK. Setup and hold requirements must be
met for proper sampling. A and C data are captured on the rising edge of DATACLK. B and D data are captured
on the falling edge of DATACLK.
For both input bus modes, a sync signal, either ISTR or SYNC, is required to sync the FIFO read and/or write
pointers.
The sync signal, either ISTR or SYNC, can be either a pulse or a periodic signal where the sync period
corresponds to multiples of eight samples. ISTR or SYNC is sampled by a rising edge in DATACLK. The pulse
duration t(ISTR_SYNC) must be at least equal to one-half of the DATACLK period.
DATA FORMAT
The 16-bit data for channels A and B is interleaved in the form A0[15:0], B0[15:0], A1[15:0], B1[15:0], A2[15:0]
into the DAB[15:0]P/N LVDS inputs. Similarly, data for channels C and D is interleaved into the DCD[15:0]P/N
LVDS inputs. Data into the DAC34SH84 is formatted according to the diagram shown in Figure 51, where index
0 is the data LSB and index 15 is the data MSB.
SAMPLE 0
SAMPLE 1
SAMPLE 2
SAMPLE 3
DAB[15:0]P/N
A0
[15:0]
B0
[15:0]
A1
[15:0]
B1
[15:0]
A2
[15:0]
B2
[15:0]
A3
[15:0]
B3
[15:0]
DCD[15:0]P/N
C0
[15:0]
D0
[15:0]
C1
[15:0]
D1
[15:0]
C2
[15:0]
D2
[15:0]
C3
[15:0]
D3
[15:0]
DATACLKP/N (DDR)
Sync
Option #1
ISTRP/N
Sync
Option #2
SYNCP/N
t(ISTR_SYNC)
t(ISTR_SYNC)
Figure 51. Data Transmission Format
T0530-01
The FIFO read and write pointer can also be synced by SIF SYNC as the third sync option if multi-device
synchronization is not needed. In this sync mode, the syncsel_fifoin(3:0) and syncsel_fifoout(3:0) in register
config32 need to be both set to 1000 for the SIF SYNC option.
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