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DAC34SH84 View Datasheet(PDF) - Texas Instruments

Part NameDescriptionManufacturer
DAC34SH84 Quad-Channel, 16-Bit, 1.5 GSPS Digital-to-Analog Converter (DAC) TI
Texas Instruments TI
DAC34SH84 Datasheet PDF : 77 Pages
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DAC34SH84
SLAS808B – FEBRUARY 2012 – REVISED JULY 2012
Register name: config38 – Address: 0x26, Default: 0xB6B6
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Register
Name
config38
Address
0x26
Bit
Name
15:0 iotest_pattern1
Function
Dataword1 in the IO test pattern. It is used with the seven other words to test the input data.
Default
Value
0xB6B6
Register name: config39 – Address: 0x27, Default: 0xEAEA
Register
Name
Address
Bit
Name
config39 0x27
15:0 iotest_pattern2
Function
Dataword2 in the IO test pattern. It is used with the seven other words to test the input
data.
Register name: config40 – Address: 0x28, Default: 0x4545
Default
Value
0xEAEA
Register
Name
Address
Bit
Name
Function
Default
Value
config40
0x28
15:0 iotest_pattern3 Dataword3 in the IO test pattern. It is used with the seven other words to test the input data. 0x4545
Register name: config41 – Address: 0x29, Default: 0x1A1A
Register
Name
Address
Bit
Name
Function
config41 0x29
15:0 iotest_pattern4 Dataword4 in the IO test pattern. It is used with the seven other words to test the input data.
Register name: config42 – Address: 0x2A, Default: 0x1616
Default
Value
0x1A1A
Register
Name Address
Bit
Name
config42 0x2A
15:0 iotest_pattern5
Function
Dataword5 in the IO test pattern. It is used with the seven other words to test the input
data.
Register name: config43 – Address: 0x2B, Default: 0xAAAA
Default
Value
0x1616
Register
Name
Address
Bit
Name
config43
0x2B
15:0 iotest_pattern6
Function
Dataword6 in the IO test pattern. It is used with the seven other words to test the input
data.
Register name: config44 – Address: 0x2C, Default: 0xC6C6
Default
Value
0xAAAA
Register
Name
config44
Address
0x2C
Bit
Name
15:0 iotest_pattern7
Function
Dataword7 in the IO test pattern. It is used with the seven other words to test the input
data.
Register name: config45 – Address: 0x2D, Default: 0x0004
Default
Value
0xC6C6
Register
Name
Address
Bit
Name
config45
0x2D
15 Reserved
14 ostrtodig_sel
13 ramp_ena
12:1 Reserved
0 sifdac_ena
Function
Reserved for factory use
When set, the OSTR signal is passed directly to the digital block. This is the signal that
is used to clock the dividers.
When set, a ramp signal is inserted in the input data at the FIFO input.
Reserved for factory use
When set, the DAC output is set to the value in sifdac(15:0) in register config48.
Default
Value
0
0
0
0000
0000
0010
0
40
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