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DAC34SH84 View Datasheet(PDF) - Texas Instruments

Part NameDescriptionManufacturer
DAC34SH84 Quad-Channel, 16-Bit, 1.5 GSPS Digital-to-Analog Converter (DAC) TI
Texas Instruments TI
DAC34SH84 Datasheet PDF : 77 Pages
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DAC34SH84
www.ti.com
Register name: config24 – Address: 0x18, Default: NA
SLAS808B – FEBRUARY 2012 – REVISED JULY 2012
Register
Name
config24
Address
0x18
Bit
15:13
12
Name
Reserved
pll_reset
11 pll_ndivsync_ena
10 pll_ena
9:8 Reserved
7:6 pll_cp(1:0)
5:3 pll_p(2:0)
2:0 pll_lfvolt(2:0)
Function
Reserved for factory use
When set, the PLL loop filter (LPF) is pulled down to 0 V. Toggle from 1 to 0 to
restart the PLL if an overspeed lockup occurs. Overspeed can happen when the
process is fast, the supplies are higher than nominal, etc., resulting in the feedback
dividers missing a clock.
When set, the LVDS SYNC input is used to sync the PLL N dividers.
When set, the PLL is enabled. When cleared, the PLL is bypassed.
Reserved for factory use
PLL pump charge select
MM 00: No charge pump
MM 01: Single pump charge
MM 10: Not used
MM 11: Dual pump charge
PLL pre-scaler dividing module control
MM 010: 2
MM 011: 3
MM 100: 4
MM 101: 5
MM 110: 6
MM 111: 7
MM 000: 8
PLL loop filter voltage. This 3-bit read-only indicator has step size of 0.4125 V. The
entire range covers from 0 V to 3.3 V. The optimal lock range of the PLL is from 010
to 101 (i.e., 0.825 V to 2.063 V). Adjust pll_vco(5:0) for optimal lock range.
Default
Value
001
0
1
0
00
00
001
NA
Register name: config25 – Address: 0x19, Default: 0x0440
Register
Name
Address
Bit
Name
config25
0x19
15:8 pll_m(7:0)
7:4 pll_n(3:0)
3:2 pll_vcoitune(1:0)
1:0 Reserved
Function
M portion of the M/N divider of the PLL.
If pll_m<7> = 0, the M divider value has the range of pll_m<6:0>, spanning from
4 to 127. (i.e., 0, 1, 2, and 3 are not valid.)
If pll_m<7> = 1, the M divider value has the range of 2 × pll_m<6:0>, spanning
from 8 to 254. (i.e., 0, 2, 4, and 6 are not valid. The M divider has even values
only.)
N portion of the M/N divider of the PLL.
MM 0000: 1
MM 0001: 2
MM 0010: 3
MM 0011: 4
MM 0100: 5
MM 0101: 6
MM 0110: 7
MM 0111: 8
MM 1000: 9
MM 1001: 10
MM 1010: 11
MM 1011: 12
MM 1100: 13
MM 1101: 14
MM 1110: 15
MM 1111: 16
PLL VCO bias tuning bits. Set to 01 for normal PLL operation
Reserved for factory use
Default
Value
0x04
0100
00
00
Copyright © 2012, Texas Instruments Incorporated
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