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DAC34SH84 View Datasheet(PDF) - Texas Instruments

Part NameDescriptionManufacturer
DAC34SH84 Quad-Channel, 16-Bit, 1.5 GSPS Digital-to-Analog Converter (DAC) TI
Texas Instruments TI
DAC34SH84 Datasheet PDF : 77 Pages
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DAC34SH84
www.ti.com
Register name: config15 – Address: 0x0F, Default: 0x0400
SLAS808B – FEBRUARY 2012 – REVISED JULY 2012
Register
Name
config15
Address
0x0F
Bit
Name
15:14
13:12
11
10:0
output_
delayAB(1:0)
output_
delayCD(1:0)
Reserved
qmc_gainD(10:0)
Function
Delays the AB data path outputs from 0 to 3 DAC clock cycles
Default
Value
00
Delays the CD data path outputs from 0 to 3 DAC clock cycles
00
Reserved for factory use
QMC gain for DACD. The full 11-bit qmc_gainD(10:0) word is formatted as UNSIGNED
with a range of 0 to 1.9990. The implied decimal point for the multiplication is between
bit 9 and bit 10.
0
100 0000
0000
Register name: config16 – Address: 0x10, Default: 0x0000 (CAUSES AUTO-SYNC)
Register
Name
config16
Address
0x10
Bit
15
14
13
12
11:0
Name
Reserved
Reserved
Reserved
Reserved
qmc_phaseAB(11:0)
Function
Reserved for factory use
Reserved for factory use
Reserved for factory use
Reserved for factory use
QMC correction phase for the AB data path. The 12-bit qmc_phaseAB(11:0) word is
formatted as 2s-complement and scaled to occupy a range of –0.5 to 0.49975 and a
default phase correction of 0.00. To accomplish QMC phase correction, this value is
multiplied by the current B sample, then summed into the A sample. If enabled in
config30, writing to this register causes an auto-sync to be generated. This
loads the values of the QMC offset registers (config12, config13, and config16)
into the QMC block at the same time. When updating the QMC values for the
AB channel, config16 should be written last. Programming config12 and
config13 does not affect the QMC settings.
Default
Value
0
0
0
0
All zeros
Register name: config17 – Address: 0x11, Default: 0x0000 (CAUSES AUTO-SYNC)
Register
Name
config17
Address
0x11
Bit
15
14
13
12
11:0
Name
Reserved
Reserved
Reserved
Reserved
qmc_phaseCD(11:0)
Function
Reserved for factory use
Reserved for factory use
Reserved for factory use
Reserved for factory use
QMC correction phase for the CD data path. The 12-bit qmc_gainCD(11:0) word is
formatted as 2s-complement and scaled to occupy a range of –0.5 to 0.49975 and
a default phase correction of 0.00. To accomplish QMC phase correction, this value
is multiplied by the current D sample, then summed into the C sample. If enabled
in config30, writing to this register causes an auto-sync to be generated. This
loads the values of the CD-channel QMC block registers (config14, config15,
and config17) into the QMC block at the same time. When updating the QMC
values for the CD-channel, config17 should be written last. Programming
config14 and config15 does not affect the QMC settings.
Default
Value
0
0
0
0
All zeros
Register name: config18 – Address: 0x12, Default: 0x0000 (CAUSES AUTO-SYNC)
Register
Name
config18
Address
0x12
Bit
Name
Function
15:0 phase_offsetAB(15:0) Phase offset added to the AB data path NCO accumulator before the generation of
the SIN and COS values. The phase offset is added to the upper 16 bits of the NCO
accumulator results, and these 16 bits are used in the sin and cos lookup tables. If
enabled in config31, writing to this register causes an auto-sync to be
generated. This loads the values of the fine mixer block registers (config18,
config20, and config21) at the same time. When updating the mixer values,
config18 should be written last. Programming config20 and config21 does not
affect the mixer settings.
Default
Value
0x0000
Copyright © 2012, Texas Instruments Incorporated
Product Folder Link(s): DAC34SH84
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