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DAC34SH84 View Datasheet(PDF) - Texas Instruments

Part NameDescriptionManufacturer
DAC34SH84 Quad-Channel, 16-Bit, 1.5 GSPS Digital-to-Analog Converter (DAC) TI
Texas Instruments TI
DAC34SH84 Datasheet PDF : 77 Pages
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DAC34SH84
www.ti.com
SLAS808B – FEBRUARY 2012 – REVISED JULY 2012
Register name: config6 – Address: 0x06, Default: No RESET Value (READ ONLY)
Register
Name
config6
Address
0x06
Bit
Name
15:8 tempdata(7:0)
7:2 Reserved
1
Reserved
0
Reserved
Function
This is the output from the chip temperature sensor. The value of this register in
2s-complement format represents the temperature in degrees Celsius. This
register must be read with a minimum SCLK period of 1 μs.
Reserved for factory use
Reserved for factory use
Reserved for factory use
Register name: config7 – Address: 0x07, Default: 0xFFFF
Default
Value
No
RESET
Value
0000 00
0
0
Register
Name
config7
Address Bit
Name
0x07 15:0 alarms_mask(15:0)
Function
These bits control the masking of the alarms. (0 = not masked, 1 = masked)
alarm_mask
Alarm That Is Masked
15
alarm_from_zerochk
14
Not used
13
alarm_fifo_collision
12
alarm_fifo_1away
11
alarm_fifo_2away
10
alarm_dacclk_gone
9
alarm_dataclk_gone
8
alarm_output_gone
7
alarm_from_iotest
6
Not used
5
alarm_from_pll
4
alarm_Aparity
3
alarm_Bparity
2
alarm_Cparity
1
alarm_Dparity
0
Not used
Register name: config8 – Address: 0x08, Default: 0x0000 (CAUSES AUTO-SYNC)
Default
Value
0xFFFF
Register
Name
Address
Bit
Name
config8
0x08
15 Reserved
14 Reserved
13 Reserved
12:0 qmc_offsetA(12:0)
Function
Reserved for factory use
Reserved for factory use
Reserved for factory use
DACA offset correction. The offset is measured in DAC LSBs. If enabled in config30,
writing to this register causes an auto-sync to be generated. This loads the values of
the QMC offset registers (config8–config9) into the offset block at the same time.
When updating the offset values for the AB channel, config8 should be written last.
Programming config9 does not affect the offset setting.
Default
Value
0
0
0
All zeros
Register name: config9 – Address: 0x09, Default: 0x8000
Register
Name
config9
Address Bit
Name
Function
0x09
15:13 fifo_offset(2:0)
12:0 qmc_offsetB(12:0)
When the sync to the FIFO occurs, this is the value loaded into the FIFO read pointer. With
this value, the initial difference between write and read pointers can be controlled. This may
be helpful in syncing multiple chips or controlling the delay through the device.
DACB offset correction. The offset is measured in DAC LSBs.
Default
Value
100
All zeros
Copyright © 2012, Texas Instruments Incorporated
Product Folder Link(s): DAC34SH84
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