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DAC34SH84 View Datasheet(PDF) - Texas Instruments

Part NameDescriptionManufacturer
DAC34SH84 Quad-Channel, 16-Bit, 1.5 GSPS Digital-to-Analog Converter (DAC) TI
Texas Instruments TI
DAC34SH84 Datasheet PDF : 77 Pages
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DAC34SH84
SLAS808B – FEBRUARY 2012 – REVISED JULY 2012
Register name: config4 – Address: 0x04, Default: No RESET Value (WRITE TO CLEAR)
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Register
Name
config4
Address
0x04
Bit
Name
15:0 iotest_results(15:0)
Function
Bits in iotest_results with a logic value of 1 tell which bit in either DAB[15:0]
bus or DCD[15:0] bus failed during the pattern checker test.
iotest_results(15:8) correspond to the data bits on both DAB[15:8] and
DCD[15:8].
iotest_results(7:0) correspond to the data bits on both DAB[7:0] and DCD[7:0].
Default
Value
No RESET
value
Register name: config5 – Address: 0x05, Default: Setup and Power-Up Conditions Dependent (WRITE TO
CLEAR)
Register Address
Name
Bit
Name
config5 0x05
15 alarm_from_zerochk
14 Reserved
13:11 alarms_from_fifo(2:0)
10 alarm_dacclk_gone
9 alarm_dataclk_gone
8 alarm_output_gone
7 alarm_from_iotest
6 Reserved
5 alarm_from_pll
4 alarm_Aparity
3 alarm_Bparity
2 alarm_Cparity
1 alarm_Dparity
0 Reserved
Function
This alarm indicates the 8-bit FIFO write pointer address has an all-
zeros pattern. Due to the pointer address being a shift register, this
is not a valid address and causes the write pointer to be stuck until
the next sync. This error is typically caused by a timing error or
improper power start-up sequence. If this alarm is asserted,
resynchronization of the FIFO is necessary. See the Power-Up
Sequence section for more detail.
Reserved for factory use
Alarm indicating FIFO pointer collisions and nearness:
MM 000: All fine
MM 001: Pointers are 2 away.
MM 01x: Pointers are 1 away.
MM 1xx: FIFO pointer collision
If the FIFO pointer collision alarm is set when collisiongone_ena is
enabled, the FIFO must be re-synchronized and the bits must be
cleared to resume normal operation.
Alarm indicating the DACCLK has been stopped.
If the bit is set when dacclkgone_ena is enabled, DACCLK must
resume and the bit must be cleared to resume normal operation.
Alarm indicating the DATACLK has been stopped.
If the bit is set when dataclkgone_ena is enabled, DATACLK must
resume and the bit must be cleared to resume normal operation.
Alarm indicating either alarm_dacclk_gone, alarm_dataclk_gone, or
alarm_fifo_collision are asserted. It controls the output. When high,
it outputs 0x8000 for each output connected to the DAC. If the bit is
set when dacclkgone_ena, dataclkgone_ena, or collisiongone_ena
are enabled, then the corresponding errors must be fixed and the
bits must be cleared to resume normal operation.
Alarm indicating the input data pattern does not match the pattern in
the iotest_pattern registers. When the data pattern checker mode is
enabled, this alarm in register config5, bit7 is the only valid alarm.
Other alarms in register config5 are not valid and can be
disregarded.
Reserved for factory use
Alarm indicating the PLL has lost lock. For version ID 001,
alarm_from_PLL may not indicate the correct status of the PLL. See
pll_lfvolt(2:0) in register config24 for proper PLL lock indication.
In dual-parity mode, an alarm indicating a parity error on the A
word. In single-parity mode, an alarm on the 32-bit data captured on
the rising edge of DATACLKP/N.
In dual-parity mode, an alarm indicating a parity error on the B
word. In single-parity mode, an alarm on the 32-bit data captured on
the falling edge of DATACLKP/N.
In dual-parity mode, an alarm indicating a parity error on the C
word.
In dual-parity mode, an alarm indicating a parity error on the D
word.
Reserved for factory use
Default
Value
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
30
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