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DAC34SH84 View Datasheet(PDF) - Texas Instruments

Part NameDescriptionManufacturer
DAC34SH84 Quad-Channel, 16-Bit, 1.5 GSPS Digital-to-Analog Converter (DAC) TI
Texas Instruments TI
DAC34SH84 Datasheet PDF : 77 Pages
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DAC34SH84
SLAS808B – FEBRUARY 2012 – REVISED JULY 2012
Register name: config1 – Address: 0x01, Default: 0x040E
www.ti.com
Register
Name
Address
Bit
Name
config1
0x01
15 iotest_ena
14 Reserved
13 Reserved
12 64cnt_ena
11 oddeven_parity
10 parity_ena
9 single_dual_parity
8 rev_interface
7 dacA_complement
6 dacB_complement
5 dacC_complement
4 dacD_complement
3 alarm_2away_ena
2 alarm_1away_ena
1 alarm_collision_ena
0 Reserved
Function
When set, enables the data pattern checker test. The outputs are
deactivated regardless of the state of TXENA and sif_txenable.
Reserved for factory use
Reserved for factory use
When set, enables resetting of the alarms after 64 good samples
with the goal of removing unnecessary errors. For instance, when
checking setup or hold through the pattern checker test, there may
initially be errors. Setting this bit removes the need for a SIF write to
clear the alarm register.
Selects between odd and even parity check
MM 0: Even parity
MM 1: Odd parity
When set, enables parity checking of each input word using the 1
PARITYP/N parity input. It should match the oddeven_parity
register setting.
When set, enables dual parity checking; otherwise, single parity
checking. The parity bit should match the oddeven_parity register
setting. parity_ena must be set for dual parity to function.
When set, the PARITY, SYNC, and ISTR inputs are rotated to allow
complete reversal of the data interface when setting the
rev_interface bit.
When rev_interface = 1, the following changes occurs
MM 1. SYNCP/N becomes ISTRP/N.
MM 2. PARITYP/N becomes SYNCP/N.
MM 3. ISTRP/N becomes PARITYP/N.
When set, the DACA output is complemented. This allows effectively
changing the + and – designations of the LVDS data lines.
When set, the DACB output is complemented. This allows effectively
changing the + and – designations of the LVDS data lines.
When set, the DACC output is complemented. This allows effectively
changing the + and – designations of the LVDS data lines.
When set, the DACD output is complemented. This allows effectively
changing the + and – designations of the LVDS data lines.
When set, the alarm from the FIFO indicating the write and read
pointers being 2 away is enabled.
When set, the alarm from the FIFO indicating the write and read
pointers being 1 away is enabled.
When set, the alarm from the FIFO indicating a collision between the
write and read pointers is enabled.
Reserved for factory use
Default
Value
0
0
0
0
0
1
0
0
0
0
0
0
1
1
1
0
28
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