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DAC34SH84 View Datasheet(PDF) - Texas Instruments

Part NameDescriptionManufacturer
DAC34SH84 Quad-Channel, 16-Bit, 1.5 GSPS Digital-to-Analog Converter (DAC) TI
Texas Instruments TI
DAC34SH84 Datasheet PDF : 77 Pages
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DAC34SH84
SLAS808B – FEBRUARY 2012 – REVISED JULY 2012
www.ti.com
Figure 50 shows the serial interface timing diagram for a DAC34SH84 read operation. SCLK is the serial interface clock input to the DAC34SH84. Serial-
data enable SDENB is an active-low input to the DAC34SH84. SDIO is serial data-in during the instruction cycle. In the three-pin configuration, SDIO is
data out from the DAC34SH84 during the data transfer cycle, whereas SDO is in a high-impedance state. In the four-pin configuration, SDO is data-out
from the DAC34SH84 during the data transfer cycle. At the end of the data transfer, SDIO and SDO output low on the final falling edge of SCLK until the
rising edge of SDENB, when SDO goes into the high-impedance state.
SDENB
SCLK
SDIO
SDO
Instruction Cycle
Data Transfer Cycle
rwb A6 A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
SDENB
SCLK
SDIO
SDO
Data n
Data n – 1
td(Data)
Figure 50. Serial-Interface Read Timing Diagram
T0522-01
24
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