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DAC34SH84 View Datasheet(PDF) - Texas Instruments

Part NameDescriptionManufacturer
DAC34SH84 Quad-Channel, 16-Bit, 1.5 GSPS Digital-to-Analog Converter (DAC) TI
Texas Instruments TI
DAC34SH84 Datasheet PDF : 77 Pages
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DAC34SH84
SLAS808B – FEBRUARY 2012 – REVISED JULY 2012
www.ti.com
Differential Nonlinearity (DNL): Defined as the variation in analog output associated with an ideal 1-LSB
change in the digital input code
Gain Drift: Defined as the maximum change in gain, in terms of ppm of full-scale range (FSR) per °C, from the
value at ambient (25°C) to values over the full operating temperature range
Gain Error: Defined as the percentage error (in FSR%) for the ratio between the measured full-scale output
current and the ideal full-scale output current
Integral Nonlinearity (INL): Defined as the maximum deviation of the actual analog output from the ideal output,
determined by a straight line drawn from zero scale to full scale
Intermodulation Distortion (IMD3): The two-tone IMD3 is defined as the ratio (in dBc) of the third-order
intermodulation distortion product to either fundamental output tone.
Offset Drift: Defined as the maximum change in dc offset, in terms of ppm of full-scale range (FSR) per °C, from
the value at ambient (25°C) to values over the full operating temperature range
Offset Error: Defined as the percentage error (in FSR%) for the ratio between the measured mid-scale output
current and the ideal mid-scale output current
Output Compliance Range: Defined as the minimum and maximum allowable voltage at the output of the
current-output DAC. Exceeding this limit may result in reduced reliability of the device or adversely affect
distortion performance.
Reference Voltage Drift: Defined as the maximum change of the reference voltage in ppm per degree Celsius
from the value at ambient (25°C) to values over the full operating temperature range
Spurious-Free Dynamic Range (SFDR): Defined as the difference (in dBc) between the peak amplitude of the
output signal and the peak spurious signal within the first Nyquist zone
Noise Spectral Density (NSD): Defined as the difference of power (in dBc) between the output tone signal
power and the noise floor of 1-Hz bandwidth within the first Nyquist zone
SERIAL INTERFACE
The serial port of the DAC34SH84 is a flexible serial interface which communicates with industry-standard
microprocessors and microcontrollers. The interface provides read/write access to all registers used to define the
operating modes of the DAC34SH84. It is compatible with most synchronous transfer formats and can be
configured as a three- or four-pin interface by sif4_ena in register config2. In both configurations, SCLK is the
serial-interface input clock and SDENB is serial-interface enable. For the three-pin configuration, SDIO is a
bidirectional pin for both data in and data out. For the four-pin configuration, SDIO is data-in only and SDO is
data-out only. Data is input into the device with the rising edge of SCLK. Data is output from the device on the
falling edge of SCLK.
Each read/write operation is framed by the serial-data enable bar (SDENB) signal asserted low. The first frame
byte is the instruction cycle which identifies the following data transfer cycle as read or write as well as the 7-bit
address to be accessed. Table 1 indicates the function of each bit in the instruction cycle and is followed by a
detailed description of each bit. The data transfer cycle consists of two bytes.
Table 1. Instruction Byte of the Serial Interface
MSB
LSB
Bit
7
6
5
4
3
2
1
0
Description
R/W
A6
A5
A4
A3
A2
A1
A0
R/W
[A6 : A0]
Identifies the following data transfer cycle as a read or write operation. A high indicates a read
operation from the DAC34SH84 and a low indicates a write operation to the DAC34SH84.
Identifies the address of the register to be accessed during the read or write operation.
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