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DAC34SH84 View Datasheet(PDF) - Texas Instruments

Part NameDescriptionManufacturer
DAC34SH84 Quad-Channel, 16-Bit, 1.5 GSPS Digital-to-Analog Converter (DAC) TI
Texas Instruments TI
DAC34SH84 Datasheet PDF : 77 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
DAC34SH84
SLAS808B – FEBRUARY 2012 – REVISED JULY 2012
www.ti.com
ELECTRICAL CHARACTERISTICS – DIGITAL SPECIFICATIONS
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
LVDS INPUTS: DAB[15:0]P/N, DCD[15:0]P/N, DATACLKP/N, ISTRP/N, SYNCP/N, PARITYCDP/N(1)
Logic-high differential
VA,B+
input voltage
200
threshold
VA,B–
Logic-low differential
input voltage
threshold
VCOM
Input common mode
1
ZT
Internal termination
85
CL
LVDS input
capacitance
fINTERL
Interleaved LVDS
data transfer rate
fDATA
Input data rate
CLOCK INPUT (DACCLKP/N)
Duty cycle
Differential voltage(2) |DACCLKP - DACCLKN|
40%
0.4
Internally biased
common-mode
voltage
Single-ended swing
level
–0.4
DACCLKP/N input
frequency
OUTPUT STROBE (OSTRP/N)
fOSTR
Frequency
Duty cycle
fOSTR = fDACCLK / (n × 8 × interp) where n is any positive
integer,
fDACCLK is DACCLK frequency in MHz
Differential voltage |OSTRP-OSTRN|
0.4
Internally biased
common-mode
voltage
Single-ended swing
level
–0.4
CMOS INTERFACE: ALARM, SDO, SDIO, SCLK, SDENB, SLEEP, RESETB, TXENA
VIH
High-level input
voltage
0.7 ×
IOVDD2
VIL
Low-level input
voltage
IIH
High-level input
current
–40
IIL
Low-level input
current
–40
CI
CMOS input
capacitance
Iload = –100 μA
VOH
ALARM, SDO, SDIO
Iload = –2 mA
IOVDD2 –
0.2
0.8 ×
IOVDD2
VOL
ALARM, SDO, SDIO
Iload = 100 μA
Iload = 2 mA
(1) See LVDS INPUTS section for terminology.
(2) Driving the clock input with a differential voltage lower than 1 V may result in degraded performance.
TYP
MAX UNIT
mV
–200 mV
1.2
1.6 V
110
135 Ω
2
pF
1500 MSPS
750 MSPS
60%
1
V
0.2
V
V
1500 MHz
50%
1.0
fDACCLK /
(8×
interp)
MHz
V
0.2
V
V
V
0.3 ×
IOVDD2
V
40 µA
40 µA
2
pF
V
V
0.2 V
0.5 V
10
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