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DAC1627D1G25 View Datasheet(PDF) - NXP Semiconductors.

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DAC1627D1G25 Datasheet PDF : 69 Pages
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NXP Semiconductors
DAC1627D1G25
Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
Table 25. Register TXCFG (address 01h) bit description …continued
Default values are shown highlighted.
Bit
Symbol
Access
Value
Description
1 to 0 INTERPOLATION[1:0]
R/W
interpolation
00
no interpolation
01
×2 interpolation
10
×4 interpolation
11
×8 interpolation
Table 26. Register PLLCFG (address 02h) bit description
Default values are shown highlighted.
Bit
Symbol
Access
Value
7
PLL_BP
R/W
0
1
6
PLL_BUF_PD
5
PLL_PLL_PD
4 to 3 PLL_DIV[1:0]
2 to 1 PLL_PHASE[1:0]
0
PLL_OSC_PD
R/W
0
1
R/W
0
1
R/W
00
01
10
11
R/W
00
01
10
11
R/W
0
1
Description
PLL bypass
DAC clock generated by PLL
DAC clock provided via external pins CLKN and
CLKP (PLL bypass mode)
PLL test buffer control
Power-down mode
enabled
PLL and CKGEN control
Power-down mode
enable
PLL divider factor
fs = 2 × fdata
fs = 4 × fdata
fs = 8 × f
undefined
PLL phase shift
0 degrees phase shift of fs
120 degrees phase shift of fs
240 degrees phase shift of fs
240 degrees phase shift of fs
PLL oscillator output power-down
Power-down mode
enabled
Table 27. Register FREQNCO_B0 (address 04h)
Default values are shown highlighted.
Bit
Symbol
Access
7 to 0 FREQ_NCO[7:0]
R/W
Value
-
Description
NCO frequency (two complement’s coding)
least significant 8 bits for the NCO frequency setting
DAC1627D1G25
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 29 April 2011
© NXP B.V. 2011. All rights reserved.
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