NXP Semiconductors
DAC1627D1G25
Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
10.7.1 CDI mode 0 (x2 interpolation)
CDI mode 0 (×2 interpolation) is required when the value of the LVDS DDR clock is twice
the internal maximum CDI frequency. Table 12 shows examples of applications using an
internal PLL or an external clock for the DAC core.
Table 12. CDI mode 0: operating modes examples
LVDS DDR
rate (MHz)
I rate;
Q rate
(Msps)
CDI
FIR mode[2]
mode[1]
SSBM
rate[3]
(Msps)
320
320
0
320
320
0
×2
640
×2
640
DAC rate
(Msps)
640
640
PLL configuration
DAC input
clock[4]
(MHz)
PLL
status[5]
PLL
divider[6]
320
enabled
2
640
disabled
n.a.
[1] Bits CDI_MODE[1:0] of register MISC_CNTRL (see Table 89).
[2] Bits INTERPOLATION[1:0] of register TXCFG (see Table 25).
[3] If a Single Sideband Modulator (SSBM) is used, see bits NCO_ON and MODULATION[2:0] of register TXCFG (see Table 25).
[4] Pins CLKP and CLKN (see Figure 2).
[5] Bit PLL_PD of register PLLCFG (see Table 26).
[6] Bits PLL_DIV[1:0] of register PLLCFG (see Table 26).
10.7.2 CDI mode 1 (x4 interpolation)
CDI mode 1 (×4 interpolation) is required when the values of the LVDS DDR clock and the
internal CDI frequency are equal. Table 13 shows examples of applications using an
internal PLL or an external clock for the DAC core.
Table 13. CDI mode 1: operating modes examples
LVDS DDR
rate (MHz)
I rate;
Q rate
(Msps)
CDI
FIR mode[2]
mode[1]
SSBM
rate[3]
(Msps)
250
250
1
250
250
1
×4
1000
×4
1000
DAC rate
(Msps)
1000
1000
PLL configuration
DAC input
clock[4]
(MHz)
PLL
status[5]
PLL
divider[6]
250
enabled
4
1000
disabled
n.a.
[1] Bits CDI_MODE[1:0] of register MISC_CNTRL (see Table 89).
[2] Bits INTERPOLATION[1:0] of register TXCFG (see Table 25).
[3] If SSBM is used, see bits NCO_ON and MODULATION[2:0] of register TXCFG (see Table 25).
[4] Pins CLKP and CLKN (see Figure 2).
[5] Bit PLL_PD of register PLLCFG (see Table 26).
[6] Bits PLL_DIV[1:0] of register PLLCFG (see Table 26).
DAC1627D1G25
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 29 April 2011
© NXP B.V. 2011. All rights reserved.
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