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DAC1627D1G25 View Datasheet(PDF) - NXP Semiconductors.

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DAC1627D1G25 Datasheet PDF : 69 Pages
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NXP Semiconductors
DAC1627D1G25
Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating
B0
A0 B0 A1 B1 A2 B2 A3 B3
PA[15..0]
LD[15..0]P/N
LVDS
RECEIVER
A0
PB[15..0]
LCLKP/N
LCLK
Fig 8. LVDS DDR receiver mapping LDAB SWAP = 1
B1
B2
B3
to DAC A
A1
A2
A3
to DAC B
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10.4.4 Input port formatting
The LVDS DDR input bus multiplexes two 16-bit streams. The LVDS receiver block
demultiplexes these two streams.
The two streams can carry two data formats:
Folded
Interleaved
The data format block is in charge of the data format adaptation (see Figure 9).
A0
A1
A0 B0 A1 B1 A2 B2 A3 B3
PA[15..0]
LD[15..0]P/N
LVDS
RECEIVER
B0
B1
PB[15..0]
LCLKP/N
LCLK
Fig 9. LVDS DDR data formats
A2
A3
B2
B3
DATA
FORMAT
I0
I1
I2
I3
to DAC A
Q0
Q1
Q2
Q3
to DAC B
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The DAC1627D1G25 can correctly decode the input stream using bit IQ_FORMAT of
register LD_CNTRL (see Table 88), because it can determine which format is used on the
LVDS DDR bus.
Table 10 shows the format mapping between the LVDS input data and the data sent to the
two DAC channels depending on the data format selected.
Table 10. Folded and interleaved format mapping
Data format
Data bit mapping
interleaved format (IQ_FORMAT = 1)
In[15..0] = An[15..0]; Qn[15..0] = Bn[15..0]
folded format (IQ_FORMAT = 0)
In[15..8] = An[15..8]; In[7..0] = Bn[15..8]
Qn[15..8] = An[7..0]; Qn[7..0] = Bn[7..0]
DAC1627D1G25
Objective data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 29 April 2011
© NXP B.V. 2011. All rights reserved.
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