DAC1627D1G25 View Datasheet(PDF) - NXP Semiconductors.

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DAC1627D1G25

Dual 16-bit DAC, LVDS interface, up to 1.25 Gsps, x2, x4 and x8 interpolating

NXP Semiconductors. 

NXP Semiconductors

DAC1627D1G25

Dual 16-bit DAC: up to 1.25 Gsps; x2, x4 and x8 interpolating

Table 5. Characteristics …continued

VDDA(1V8) = 1.8 V; VDDD(1V8) = 1.8 V; VDDA(3V3) = 3.3 V; Typical values measured at Tamb = +25 °C; RL = 50 Ω; IO(fs) = 20 mA;

maximum sample rate used; external PLL; no auxiliary DAC; no inverse sinus x/x; no output correction; output load condition

defined in Figure 22; output level = 1 V (p-p).

Symbol

Parameter

Conditions

Test Min

Typ

[1]

Max

Unit

ACPR

NSD

adjacent channel fs = 1228.8 Msps;

power ratio

×4 interpolation;

fo = 210 MHz

1 carrier; BW = 5 MHz

D

-

2 carriers; BW = 10 MHz D

-

4 carriers; BW = 20 MHz D

-

noise spectral

density

fs = 983.04 Msps;

×4 interpolation;

D

-

fo = 20 MHz at −1 dBFS

fs = 983.04 Msps;

×4 interpolation;

D

-

fo = 153.6 MHz at −1 dBFS

77

-

73

-

72

-

-164

-

-161

-

dBc

dBc

dBc

dBm/Hz

dBm/Hz

[1] D = guaranteed by design; C = guaranteed by characterization; I = 100 % industrially tested.

[2] VDDA(1V8)_D, VDDA(1V8)_P1 and VDDA(1V8)_P2 must be connected to the same 1.8 V analog power supply. it is recommended to use

dedicated filters for the three power pins.

[3] |Vgpd| represents the ground potential difference voltage. This voltage is the result of current flowing through the finite resistance and the

inductance between the receiver and the driver circuit ground voltages.

10. Application information

10.1 General description

The DAC1627D1G25 is a dual 16-bit DAC operating up to 1250 Msps. Each DAC consists

of a segmented architecture, comprising a 6-bit thermometer sub-DAC and a 10-bit binary

weighted sub-DAC.

A maximum input LVDS DDR data rate of up to 312.5 MHz and a maximum output

sampling rate of 1250 Msps ensure more flexibility for wide bandwidth and multi-carrier

systems. The internal 40-bit NCO of the DAC1627D1G25 simplifies the frequency

selection of the system. The DAC1627D1G25 provides ×2, ×4 or ×8 interpolation filters

that are very useful for removing the undesired images.

Each DAC generates two complementary current outputs on pins IOUTAP and IOUTAN

and pins IOUTBP and IOUTBN. These outputs provide a full-scale output current (IO(fs)) of

up to 31.8 mA. An internal reference is available for the reference current which is

externally adjustable using pin VIRES.

High resolution internal gain, phase and offset control provide outstanding image and

Local Oscillator (LO) signal rejection at the system analog modulator output.

Multiple device synchronization enables synchronization of the outputs of multiple DAC

devices. MDS guarantees a maximum skew of one output clock period between several

devices.

All functions can be set using an SPI interface.

DAC1627D1G25

Objective data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 1 — 29 April 2011

© NXP B.V. 2011. All rights reserved.

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