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DAC08GBC View Datasheet(PDF) - Analog Devices

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DAC08GBC Datasheet PDF : 12 Pages
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DAC08
range, negative logic input range and negative logic threshold
range; consult the various figures for guidance. For example,
operation at 4.5 V with IREF = 2 mA is not recommended
because negative output compliance would be reduced to near
zero. Operation from lower supplies is possible; however, at
least 8 V total must be applied to ensure turn-on of the internal
bias network.
Symmetrical supplies are not required, as the DAC08 is quite
insensitive to variations in supply voltage. Battery operation is
feasible as no ground connection is required: however, an artificial
ground may be used to ensure logic swings, etc., remain
between acceptable limits.
Power consumption may be calculated as follows:
PD = (I+) (V+) + (I–) (V–)
A useful feature of the DAC08 design is that supply current is
constant and independent of input logic states; this is useful in
cryptographic applications and further serves to reduce the size
of the power supply bypass capacitors.
TEMPERATURE PERFORMANCE
The nonlinearity and monotonicity specifications of the DAC08
are guaranteed to apply over the entire rated operating temperature
range. Full-scale output current drift is low, typically ±10 ppm/°C,
with zero-scale output current and drift essentially negligible
compared to 1/2 LSB.
The temperature coefficient of the reference resistor R14 should
match and track that of the output resistor for minimum overall
full-scale drift. Settling times of the DAC08 decrease approxi-
mately 10% at 55°C; at +125°C an increase of about 15%
is typical.
The reference amplifier must be compensated by using a capacitor
from pin 16 to V. For fixed reference operation, a 0.01 µF
capacitor is recommended. For variable reference applications,
see Reference Amplifier Compensation for Multiplying Applica-
tionssection.
MULTIPLYING OPERATION
The DAC08 provides excellent multiplying performance with an
extremely linear relationship between IFS and IREF over a range
of 4 µA to 4 mA. Monotonic operation is maintained over a
typical range of IREF from 100 µA to 4.0 mA.
SETTLING TIME
The DAC08 is capable of extremely fast settling times, typically
85 ns at IREF = 2.0 mA. Judicious circuit design and careful
board layout must be employed to obtain full performance
potential during testing and application. The logic switch design
enables propagation delays of only 35 ns for each of the 8 bits.
Settling time to within 1/2 LSB of the LSB is therefore 35 ns,
with each progressively larger bit taking successively longer. The
MSB settles in 85 ns, thus determining the overall settling time
of 85 ns. Settling to 6-bit accuracy requires about 65 ns to 70 ns.
The output capacitance of the DAC08 including the package is
approximately 15 pF, therefore the output RC time constant
dominates settling time if RL > 500 .
Settling time and propagation delay are relatively insensitive to
logic input amplitude and rise and fall times, due to the high
gain of the logic switches. Settling time also remains essentially
constant for IREF values. The principal advantage of higher IREF
values lies in the ability to attain a given output level with lower
load resistors, thus reducing the output RC time constant.
Measurement of settling time requires the ability to accurately
resolve ± 4 µA, therefore a 1 kload is needed to provide
adequate drive for most oscilloscopes. The settling time fix-
ture shown in schematic labelled Settling Time Measurement
uses a cascade design to permit driving a 1 kload with less
than 5 pF of parasitic capacitance at the measurement node. At
IREF values of less than 1.0 mA, excessive RC damping of the
output is difficult to prevent while maintaining adequate sensi-
tivity. However, the major carry from 01111111 to 10000000
provides an accurate indicator of settling time. This code change
does not require the normal 6.2 time constants to settle to
within ± 0.2% of the final value, and thus settling times may be
observed at lower values of IREF.
DAC08 switching transients or glitchesare very low and may
be further reduced by small capacitive loads at the output at a
minor sacrifice in settling time.
Fastest operation can be obtained by using short leads, minimizing
output capacitance and load resistor values, and by adequate
bypassing at the supply, reference, and VLC terminals. Supplies
do not require large electrolytic bypass capacitors as the supply
current drain is independent of input logic states; 0.1 µF capacitors
at the supply pins provide full transient protection.
REV. B
VCL
0.7V
+VREF
0.1F
FOR TURN-ON, VL = 2.7V
FOR TURN-OFF, VL = 0.7V
VL
1k
MINIMUM
CAPACITANCE
Q1
VIN
1F
1k
+5V
50F
1F
Q2
VOUT 1X
PROBE
RREF
R15
14 5
15
6 7 8 9 10 11 12
4
DAC08
2
13
3 16
0.01F
IOUT
100k2k
15k
15V
+0.4V
0V
0V
0.4V
0.1F
0.1F
+15V 15V
0.1F
Figure 17. Settling Time Measurement
–11–
 

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