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SA7026DK View Datasheet(PDF) - Philips Electronics

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SA7026DK Datasheet PDF : 14 Pages
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Philips Semiconductors
1.3GHz low voltage fractional-N dual synthesizer
Objective specification
SA7026
Auxiliary Output Charge Pumps
The auxiliary charge pumps on pin PHA are driven by the auxiliary phase detector and the current value is determined by the external resistor
attached to pin Rset.
Main and auxiliary chargepump currents
CP1
CP0
0
0
IPHA
1.5xlset
IPHP
3xIset
IPHP–SU
15xlset
0
1
0.5xlset
1xlset
5xlset
1
0
1.5xlset
3xlset
15xlset
1
1
0.5xlset
1xlset
5xlset
NOTES
1. ISET = Vset/Rset: bias current for charge pumps.
2. CP1 is used to disable the PHI pump, IPHP_SU is the total current at pin PHP during speed up condition.
IPHI
36xlset
12xlset
0
0
Lock Detect
The output LOCK maintains a logic ‘1’ when the auxiliary phase
detector ANDed with the main phase detector indicates a lock
condition. The lock condition for the main and auxiliary synthesizers
is defined as a phase difference of less than "1 period of the
frequency at the input REFin+, –. One counter can fulfill the lock
condition when the other counter is powered down. Out of lock (logic
’0’) is indicated when both counters are powered down.
Power-down mode
The power-down signal can be either hardware (PON) or software
(PD). The PON signal is exclusively ORed with the PD bits. If
PON = 0, then the part is powered up when PD = 1. PON can be
used to invert the polarity of the software bit PD. When the
synthesizer is reactivated after the power-down the main and
reference dividers are synchronized to avoid possibility of random
phase errors on power-up.
1998 Oct 13
10
 

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