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FC80960HD66SL2GN View Datasheet(PDF) - Intel

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FC80960HD66SL2GN Datasheet PDF : 102 Pages
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80960HA/HD/HT
Table 23. AC Characteristics Notes
NOTES:
1. See Section 4.8, “AC Timing Waveforms” on page 38 for waveforms and definitions.
2. See Figure 25 “Output Delay or Hold vs. Load Capacitance” on page 44 for capacitive derating information
for output delays and hold times.
3. See Figure 22 “Rise and Fall Time Derating at 85°C and Minimum VCC” on page 43 for capacitive derating
information for rise and fall times.
4. Where N is the number of NRAD, NRDD, NWAD or NWDD wait states that are programmed in the Bus
Controller Region Table. WAIT never goes active when there are no wait states in an access.
5. N = Number of wait states inserted with READY.
6. These specifications are guaranteed by the processor.
7. These specifications must be met by the system for proper operation of the processor.
8. RESET is an asynchronous input that has no required setup and hold time for proper operation. However,
to guarantee the device exits the reset mode synchronized to a particular clock edge, the rising edge of
RESET must meet setup and hold times to the rising edge of the CLKIN.
9. The interrupt pins are synchronized internally by the 80960Hx. They have no required setup or hold times
for proper operation. These pins are sampled by the interrupt controller every clock and must be active for
at least two consecutive CLKIN rising edges when asserting them asynchronously. To guarantee
recognition at a particular clock edge, the setup and hold times shown must be met.
10.Relative Output timings are not tested.
11.Not tested.
12.The processor minimizes changes to the bus signals when transitioning from a bus cycle to an idle bus for
the following signals: A31:4, SUP, CT3:0, D/C, LOCK, W/R, BE3:0.
Table 24. 80960Hx Boundary Scan Test Signal Timings
Symbol
Parameter
Min Max
TBSF
TBSC
TBSCH
TBSCL
TBSCR
TBSCF
TBSIS1
TCK Frequency
TCK Period
TCK High Time
TCK Low Time
TCK Rise Time
TCK Fall Time
Input Setup to TCK —
TDI, TMS
0
8
125 Infinite
40
40
8
8
8
TBSIH1
Input Hold from TCK —
TDI, TMS
10
TBSOV1
TBSOF1
TBSOV2
TDO Valid Delay
TDO Float Delay
All Outputs (Non-Test)
Valid Delay
3
30
36
3
30
TBSOF2
All Outputs (Non-Test)
Float Delay
36
TBSIS2
Input Setup to TCK - All
Inputs (Non-Test)
8
TBSIH2
Input Hold from TCK - All 10
Inputs (Non-Test)
NOTE:
1. Not tested.
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Measured at 1.5 V (1)
Measured at 1.5 V (1)
0.8 V to 2.0 V (1)
2.0 V to 0.8 V (1)
(1)
Relative to TCK
Relative to TCK (1)
36
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