CXP85112B/85116B, CXP85220A/85224A/85228A/85232A
(2) Serial transfer
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Item
SCK cycle time
SCK High and Low level
widths
SI input setup time
(for SCK ↑)
SI input hold time
(for SCK ↑)
SCK ↓ → SO delay time
Symbol Pins
tKCY
SCK
tKH
tKL
SCK
tSIK
SI
tKSI
SI
tKSO
SO
Conditions
Input mode
Output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
SCK input mode
SCK output mode
Min.
1000
8000/fc
400
4000/fc – 50
100
200
200
100
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
200
ns
100
ns
Note) The load condition for the SCK output mode, SO output delay time is 50pF + 1TTL.
SCK
tKCY
tKL
tKH
tSIK
tKSI
0.8VDD
0.2VDD
0.8VDD
SI
Input data
0.2VDD
tKSO
0.8VDD
SO
Output data
0.2VDD
Fig. 4. Serial transfer timing
– 13 –