CXP85112B/85116B, CXP85220A/85224A/85228A/85232A
AC Characteristics
(1) Clock timing
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Item
Symbol Pins
Conditions
Min.
Max. Unit
System clock frequency fC
XTAL
EXTAL
Fig. 1, Fig. 2
3.5
4.5
MHz
System clock input
pulse width
tXL,
tXH
EXTAL
Fig. 1, Fig. 2
External clock drive
100
ns
System clock input rise
time, fall time
tCR,
tCF
EXTAL
Fig. 1, Fig. 2
External clock drive
200
ns
Event clock input clock
pulse width
tEH,
tEL
EC
Fig. 3
tsys + 50∗1
ns
Event count input clock tER,
rise time, fall time
tEF
EC
Fig. 3
20
ms
∗1 tsys indicates the three values below according to the upper two bits (CPU clock selection) of the clock
control register (address: 00FEH).
tsys [ns] = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11")
EXTAL
1/fc
tXH
tCF
tXL
Fig. 1. Clock timing
VDD – 0.4V
0.4V
tCR
Crystal oscillation
Ceramic oscillation
External clock
EXTAL XTAL
C1
C2
EXTAL XTAL
OPEN
Fig. 2. Clock applying condition
0.8VDD
EC
0.2VDD
tEH
tEF
tEL
tER
Fig. 3. Event count clock timing
– 12 –