CXP82952 View Datasheet(PDF) - Sony Semiconductor
Part Name
Description
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CXP82952 Datasheet PDF : 24 Pages
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CXP82940/82948/82952/82960
(5) I2C bus timing
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Item
Symbol
Pin
Condition Min. Max. Unit
SCL clock frequency
fSLC
SCL
0
100 kHz
Bus-free time before starting transfer
tBUF
SDA, SCL
4.7
µs
Hold time for starting transfer
tHD; STA
SDA, SCL
4.0
µs
Clock Low level width
tLOW
SCL
4.7
µs
Clock High level width
tHIGH
SCL
4.0
µs
Setup time for repetitive transfers
Data hold time
tSU; STA
tHD; DAT
SDA, SCL
SDA, SCL
4.7
µs
0∗
µs
Data setup time
tSU; DAT
SDA, SCL
250
ns
SDA, SCL rise time
tR
SDA, SCL
1
µs
SDA, SCL fall time
tF
SDA, SCL
300 ns
Setup time for transfer completion
tSU; STO
SDA, SCL
4.7
µs
∗ The data hold time must exceed 300ns because the SCL rise time (300ns max.) is not taken into consideration.
Fig.10. I2C bus transfer timing
SDA
SCL
tBUF
tR
tHD ; STA
P
S
tLOW
tF
tHD ; DAT
tHIGH
tSU ; DAT
tHD ; STA
tSU ; STA
tSU ; STO
St
P
Fig.11. Recommended circuit example for I2C device
I2C
device
I2C
device
RS
RS RS
RS RP
RP
SDA0
(or SDA1)
SCL0
(or SCL1)
• Pull-up resistors (RP) must be connected to SDA0 (or SDA1) and SCL0 (or SCL1).
• Serial resistance (Rs = 300Ω or less) of SDA0 (or SDA1) and SCL0 (SCL1) reduces spike noise caused by
CRT flash-over.
– 21 –
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