CXP82832/82840/82852/82860
Pin
PE6/PWM
1 pin
PE7/TO/ADJ
1 pin
PD0/A55
to
PD7/A48
PF0/A47
to
PF7/A40
PG0/A39
to
PG7/A32
PH0/A31
to
PH7/A24
32 pins
Port E
PWM
Circuit format
Port E output selection
"0" when reset
Port E data
"1" when reset
Output enable
Data bus
RD (Port E)
When reset
High level
Port E
Internal reset signal
Port E data
00
"1" when reset TO 01
MPX
ADJ16K∗1 10
∗2
ADJ2K∗2 11
Port E output selection (upper)
Port E output selection (lower)
"00" when reset
TO output enable
∗1 ADJ signal is a frequency dividing
output for 32kHz oscillation frequency adjustment.
ADJ2 can be used for buzzer output.
∗2 Pull-up transistor approx. 150kΩ
High level
(with approx.
150kΩ
resistor when
reset)
Port D
Port F
Port G
Port H
Segment output data
Output selection control signal
∗
("0" when reset)
Port D, F, G and H data
"0" when reset
OP
Pull-down resistor
Mask
option
VFDP
Data bus
RD (Ports D, F, G and H)
∗ High voltage drive transistor
Hi-Z or Low
level (when
PD resistor is
connected)
–8–