CXP82840 View Datasheet(PDF) - Sony Semiconductor
Part Name
Description
View to exact match
CXP82840 Datasheet PDF : 22 Pages
| |||
CXP82832/82840/82852/82860
(2) Serial transfer (CH0)
(Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Item
CS0 ↓ → SCK0
delay time
CS0 ↑ → SCK0
float delay time
CS0 ↓ → SO0
delay time
CS0 ↑ → SO0
float delay time
CS0 High level width
SCK0 cycle time
SCK0
High, Low level width
SI0 input set-up time
(for SCK0 ↑)
SI0 input hold time
(for SCK0 ↑)
SCK0 ↓ → SO0
delay time
Symbol Pin
Condition
Min.
Max. Unit
tDCSK
SCK0
Chip select transfer mode
(SCK0 = output mode)
tsys + 200 ns
tDCSKF SCK0
Chip select transfer mode
(SCK0 = output mode)
tsys + 200 ns
tDCSO SO0 Chip select transfer mode
tsys + 200 ns
tDCSOF SO0 Chip select transfer mode
tsys + 200 ns
tWHCS CS0 Chip select transfer mode tsys + 200
ns
Input mode
2tsys + 200
ns
tKCY SCK0
Output mode
16000/fc
ns
tKH
tKL
Input mode
SCK0
Output mode
tsys + 100
8000/fc – 50
ns
ns
SCK0 input mode
100
ns
tSIK
SI0
SCK0 output mode
200
ns
SCK0 input mode
tsys + 200
ns
tKSI
SI0
SCK0 output mode
100
ns
SCK0 input mode
tKSO SO0
SCK0 output mode
tsys + 200 ns
100
ns
Note 1) tsys indicates the three values below according to the upper two bits (CPU clock selection) of the
control clock registor (CLC: 00FEH).
tsys (ns) = 2000/fc (upper two bits = "00"), 4000/fc (upper two bits = "01"), 16000/fc (upper two bits = "11")
Note 2) The load condition for the SCK0 output mode, SO0 output delay time is 50pF + 1TTL.
– 15 –
|
|
Share Link: 