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CXK5T16100TM View Datasheet(PDF) - Sony Semiconductor

Part NameDescriptionManufacturer
CXK5T16100TM 65536-word × 16-bit High Speed CMOS Static RAM Sony
Sony Semiconductor Sony
CXK5T16100TM Datasheet PDF : 10 Pages
1 2 3 4 5 6 7 8 9 10
CXK5T16100TM
• Read cycle (WE = “H”)
Item
VCC = 2.7 to 3.6V VCC = 3.3V ± 0.3V
Symbol
Unit
Min. Max. Min. Max.
Read cycle time
tRC
120
100
ns
Address access time
Chip enable access time (CE)
tAA
120
100 ns
tCO
120
100 ns
Byte enable access time (UB, LB)
Output enable to output valid
tBO
60
50
ns
tOE
60
50
ns
Output hold from address change
tOH
10
10
ns
Chip enable to output in low Z (CE)
tLZ
10
10
ns
Output enable to output in low Z (OE)
tOLZ
5
5
ns
Byte enable to output in low Z (UB, LB) tBLZ
5
5
ns
Chip disable to output in high Z (CE)
tHZ1
40
40
ns
Chip disable to output in high Z (OE)
tOHZ1
35
35
ns
Byte disable to output in high Z (UB, LB) tBHZ1
35
35
ns
1 tHZ, tOHZ and tBHZ are defined as the time required for outputs to turn to high impedance state and are not
referred to as output voltage levels.
• Write cycle
Item
VCC = 2.7 to 3.6V VCC = 3.3V ± 0.3V
Symbol
Unit
Min. Max. Min. Max.
Write cycle time
tWC
120
100
ns
Address valid to end of write
tAW
100
80
ns
Chip enable to end of write
tCW
100
80
ns
Byte enable to end of write
tBW
100
80
ns
Data to write time overlap
tDW
50
40
ns
Data hold from write time
tDH
0
0
ns
Write pulse width
tWP
70
70
ns
Address setup time
tAS
0
0
ns
Write recovery time (WE)
tWR
5
5
ns
Write recovery time (CE, UB, LB)
tWR1
5
5
ns
Output active from end of write
Write to output in high Z
tOW
5
5
ns
tWHZ2
40
40
ns
2 tWHZ is defined as the time required for outputs to turn to high impedance state and is not referred to as
output voltage levels.
–5–
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