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TSA5527AT View Datasheet(PDF) - Philips Electronics

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TSA5527AT Datasheet PDF : 28 Pages
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Philips Semiconductors
1.3 GHz universal bus-controlled
TV synthesizers
Product speciļ¬cation
TSA5526; TSA5527
PINNING
SYMBOL PIN
DESCRIPTION
RF
1 RF signal input
VEE
VCC1
VCC2
BS4
2 ground
3 supply voltage (+5 V)
4 band switch supply voltage (+12 V)
5 PNP band switch buffer output 4
BS3
6 PNP band switch buffer output 3
BS2
7 PNP band switch buffer output 2
BS1
8 PNP band switch buffer output 1
CP
9 charge-pump output
Vtune
SW
10 tuning voltage output
11 bus format selection input, I2C-bus
or 3-wire
LOCK/ADC 12 lock detector output (3-wire bus/
ADC input (I2C-bus)
SCL
13 serial clock input
SDA
14 serial data input/output
CE
15 chip enable/address selection input
XTAL
16 crystal oscillator input
handbook, halfpage
RF 1
16 XTAL
VEE 2
VCC1 3
VCC2 4
BS4 5
15 CE
14 SDA
TSA5526 13 SCL
TSA5527 12 LOCK/ADC
BS3 6
11 SW
BS2 7
BS1 8
10 Vtune
9 CP
MBE326
Fig.2 Pin configuration.
FUNCTIONAL DESCRIPTION
The device is controlled via the I2C-bus or the 3-wire bus
depending on the voltage applied to the SW input (pin 11).
A HIGH level on the SW input enables the 3-wire bus
inputs which are CE (Chip Enable), SDA (serial data input)
and SCL (serial clock input). A LOW level on the SW input
enables the I2C-bus inputs which are AS (Address
Selection input), SDA (serial data input/output) and SCL
(serial clock input). The bus format selection is given in
Table 2.
I2C-bus mode (SW = LOW); see Table 3
WRITE MODE (R/W = 0)
Data bytes can be sent to the device after the address
transmission (first byte). Four data bytes are required to
fully program the device. The bus transceiver has an
auto-increment facility which permits the programming of
the device within one single transmission
(address + 4 data bytes).
The device can also be partially programmed providing
that the first data byte following the address is Divider
Byte 1 (DB1) or the Control Byte (CB). The bits in the data
bytes are defined in Table 3.
The first bit of the first data byte transmitted indicates
whether frequency data (first bit = logic 0) or control and
band switch data (first bit = logic 1) will follow. Until an
I2C-bus STOP command is sent by the controller,
additional data bytes can be entered without the need to
readdress the device. The frequency register is loaded
after the 8th clock pulse of the second Divider Byte (DB2),
the control register is loaded after the 8th clock pulse of the
Control Byte (CB) and the band switch register is loaded
after the 8th clock pulse of the Band switch Byte (BB).
I2C-BUS ADDRESS SELECTION
The module address contains programmable address bits
(MA1 and MA0) which offer the possibility of having
several synthesizers (up to 3) in one system by applying a
specific voltage to the CE input.
The relationship between MA1 and MA0 and the input
voltage applied to the CE input is given in Table 5.
1996 Sep 24
6
 

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