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TSA5526M View Datasheet(PDF) - Philips Electronics

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TSA5526M Datasheet PDF : 28 Pages
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Philips Semiconductors
1.3 GHz universal bus-controlled
TV synthesizers
Product specification
TSA5526; TSA5527
GENERAL DESCRIPTION
The device is a single-chip PLL frequency synthesizer
designed for TV and VCR tuning systems. The circuit
consists of a divide-by-eight prescaler with its own
preamplifier, a 15-bit programmable divider, a crystal
oscillator and its programmable reference divider and a
phase/frequency detector combined with a charge-pump
which drives the tuning amplifier and the 33 V output.
Four high-current PNP band switch buffers are provided
for band switching. Two PNP buffers can be switched on
simultaneously. The sum of the collector currents is limited
to 50 mA.
Depending on the reference divider ratio (512, 640 or
1024), the phase comparator operates at 3.90625 kHz,
6.25 kHz or 7.8125 kHz using a 4 MHz crystal.
The device can be controlled in accordance with the
I2C-bus format or the 3-wire bus format depending on the
voltage applied to the SW input (see Table 2). In the 3-wire
bus mode (SW = HIGH) pin 12 is the LOCK output.
The lock output is LOW when the PLL loop is locked. In the
I2C-bus mode (SW = LOW) the LOCK detector bit FL is set
to logic 1 when the loop is locked and is read on the SDA
line (status byte) during a read operation. The ADC input
is available on pin 12 for AFC control in the I2C-bus mode
only. The ADC code is read during a read operation on the
I2C-bus. In the test mode pin 12 is used as a test output for
fref and 12fdiv in the I2C-bus mode and the 3-wire bus mode
(see Table 6).
When the automatic charge-pump current switch mode is
activated, depending on the device given in Table 6, and
when the loop is phase-locked, the charge-pump current
value is automatically switched to LOW.
This action is taken to improve the carrier-to-noise ratio.
The status of this feature can be read in the ACPS flag
during a read operation on the I2C-bus (see Table 8).
I2C-bus format (SW = LOW)
Five serial bytes (including address byte) are required to
address the device, select the VCO frequency, program
the four PNP band switch buffers, set the charge-pump
current and the reference divider ratio.
The device has three independent I2C-bus addresses
which can be selected by applying a specific voltage on the
CE input (see Table 5). The general address C2 is always
valid. When the I2C-bus format is fully used, TSA5526 and
TSA5527 are equal.
3-wire bus format (SW = VCC1 or open-circuit)
Data is transmitted to the device during a HIGH level on
the CE input (enable line pin 15). The device is compatible
with 18-bit and 19-bit data formats. The first four bits are
used to program the PNP band switch buffers and the
remaining bits are used to control the programmable
divider. A 27-bit data format may also be used to set the
charge-pump current, the reference divider ratio and for
test purposes. The differences between TSA5526 and
TSA5527 are given in Table 1.
When the 27-bit format is used, the TSA5526 and
TSA5527 are equal and the reference divider is controlled
by the RSA and RSB bits (see Table 7 and
Figs 3, 4 and 5).
Table 1 Differences between TSA5526 and TSA5527
TYPE NUMBER
TSA5526
TSA5526
TSA5527
DATA WORD
18-bit
19-bit
19-bit
REFERENCE DIVIDER
512(1)
1 024(1)
640(2)
FREQUENCY STEP (kHz)
62.5
31.25
50
Notes
1. The selection of the reference divider is given by an automatic identification of the data word length.
2. The reference divider is set to 640 at power-on reset.
1996 Sep 24
4
 

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