TSA5526AM View Datasheet(PDF) - Philips Electronics

Part Name

Description

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TSA5526AM

1.3 GHz universal bus-controlled TV synthesizers

Philips Electronics 

Philips Semiconductors

1.3 GHz universal bus-controlled

TV synthesizers

Product specification

TSA5526; TSA5527

Table 16 Two status byte acquisition

S

C3

A

XX(1)

A

XX(1)

X(2)

P

Notes

1. XX = the read status byte.

2. X = no acknowledge from the master means end of sequence.

Other I2C-bus addresses may be selected by applying an appropriate voltage to the CE input.

Examples of 3-wire bus sequences (TSA5526; SW = OPEN)

Table 17 18-bit sequence (fosc = 800 MHz, BS4 = ON)

100011001000000000

The reference divider is automatically set to 512 unless RSB has been programmed to 0 during a 27-bit sequence

(see Table 19).

Table 18 19-bit sequence (fosc = 650 MHz, BS3 = ON)

0100101000101000000

The reference divider is automatically set to 1024 unless RSB has been programmed to 0 during a 27-bit sequence

(see Table 19).

Table 19 27-bit sequence (fosc = 750 MHz, BS1 = ON, N = 640, Icp = 60 µA, no test function)

000101110101001100010001000

Table 20 19-bit sequence

0001010111011100000

This sequence will program fosc to 600 MHz in 50 kHz steps. ICP remains at 60 µA.

Table 21 18-bit sequence

000110111011100000

This sequence will program fosc to 600 MHz in 50 kHz steps. ICP remains at 60 µA.

Table 22 27-bit sequence (fosc = 650 MHz, BS1 = ON)

000110100010100000011001010

This sequence sets RSA to 0, RSB to 1 and CP to 1. After this sequence ICP = 280 µA, N = 1024 (19-bit transmission)

and N = 512 (18-bit transmission), RSB = 1.

1996 Sep 24

18

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