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CT1820-001-2 View Datasheet(PDF) - Aeroflex Corporation

Part Name
Description
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CT1820-001-2
Aeroflex
Aeroflex Corporation Aeroflex
CT1820-001-2 Datasheet PDF : 14 Pages
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SELF TEST FUNCTION
A high on the S/T SELECT input sets the hybrid in the SELF
TEST mode. In this mode, the DATA and DATA output lines
are connected to the Decoder inputs so that the unit may
operate in the "wraparound" mode without actually going
through the data bus transceiver. Note that the DATA and
DATA output lines are active in this mode and the S/T
SELECT command must also be used to inhibit the data bus
transmitter to prevent arbitrary transmission on the data
bus.
TERMINAL FAIL SAFE
In order to satisfy the Terminal Fail Safe requirements of
MIL-STD-1553B, the DATA and DATA output lines are
continuously monitored for length of message. A
transmitted message in excess of 768μs sets the FAIL SAFE
output high and terminates the transmission by setting both
DATA and DATA output lines low. As a redundant safety
factor, the FAlLSAFE output may be applied to the lNHlBlT
input of the data bus transmitter (if so equipped). Further
transmissions are prevented until the FAIL SAFE flag is reset
either by reception of a valid command word containing the
terminal address or by a negative pulse on the MRST input.
Note: Transmissions containing gaps of 3μs or less are
considered continuous, even if the gap is caused by a MRST
pulse.
TERMINAL ADDRESS LINES
The five-bit terminal address is set by hard wiring the 5-BlT
ADDRESS lines. The hybrid contains internal pull-up
resistors so that logic "1" lines may be left open circuited.
Logic "0" lines must be grounded.
In operation, RT ENABLE goes high when a valid command
word containing the hard-wired address is received. See
"RECEIVE CYCLE OPERATION" for timing.
OSCILLATOR AND CLOCK DRIVER
The hybrid may be operated with either the internal clock
or an external clock source.
For internal clock operation, a 12MHz parallel-resonant
fundamental-mode crystal must be connected from XTAL
to ground. Power (+5V) must be applied to +5V
OSC/CLOCK POWER and CLOCK OUT must be connected
to CLOCK IN.
For external clock operation, no power is applied to +5V
OSC/CLOCK POWER and the external clock is applied to
CLOCK IN (CLOCK OUT not connected). The external clock
must be capable of driving a 20 picofarad load to within 0.5
volts of VCC and within 0.5 volts of ground with rise and fall
times of less than 10 nanoseconds. Standard TTL levels are
not satisfactory. For a normal 1MHz data rate, the clock
frequency must be 12MHz.
FALSE RT ENABLE
Terminals that continuously monitor their own
transmissions are subject to "END-AROUND" operation
due to a false RT ENABLE. The terminal can erroneously
interpret its own status word as a new command word. If no
measures are taken to prevent or re-set RT ENABLE, it will
remain high for 20μs or until the DECODER recognises a
new valid sync (whichever time is shorter).
RT ENABLE may be inhibited by interrupting the RECEIVE
CYCLE during a status word transmission. Inverted SEND
DATA applied to DEC RST will prevent reception of the
status word.
If continuous monitoring is required, RT ENABLE may be
reset immediately after it goes high by a 1μs (minimum) low
at DEC RST. The status word will then be available at the
second-rank receive register.
SCDCT1820 Rev F 4/10/08
10
Aeroflex Plainview
 

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