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CS4294 View Datasheet(PDF) - Cirrus Logic

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CS4294 Datasheet PDF : 42 Pages
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CS4294
SERIAL PORT TIMING
Parameter
Symbol Min
RESET# Timing
Vdd stable to RESET# inactive
RESET# active low pulse width
RESET# inactive to BIT_CLK start-up delay
1st SYNC active to CODEC READY set
Clocks
Tvdd2rst#
5
Trst_low
1.0
Trst2clk
25
Tsync2crd
-
BIT_CLK frequency
BIT_CLK period
BIT_CLK output jitter (depends on XTAL_IN source)
Fclk
-
Tclk_period
-
-
BIT_CLK high pulse width
BIT_CLK low pulse width
SYNC frequency
SYNC period
SYNC high pulse width
SYNC low pulse width
Data Setup and Hold
Tclk_high
36
Tclk_low
36
Fsync
-
Tsync_period
-
Tsync_high
-
Tsync_low
-
Output Propagation delay from rising edge of BIT_CLK
Tco
-
Input setup time from falling edge of BIT_CLK
Tisetup
10
Input hold time from falling edge of BIT_CLK
Tihold
0
Input Signal rise time
Tirise
2
Input Signal fall time
Tifall
2
Output Signal rise time
(Note 5, 6) Torise
2
Output Signal fall time
(Note 5, 6) Tofall
2
Misc. Timing Parameters
End of Slot 2 to BIT_CLK, SDATA_IN low (PR4)
SYNC pulse width (PR4) Warm Reset
SYNC inactive (PR4) to BIT_CLK start-up delay
Setup to trailing edge of RESET# (test mode)
Rising edge of RESET# to Hi-Z delay
(Note 5)
(Note 5)
Ts2_pdown
Tsync_pr4
Tsync2clk
Tsetup2rst
Toff
-
1.1
162.8
15
-
Notes: 6. BIT_CLK measured with 47 series termination and CL = 50 pF.
Typ
.
-
120
62.4
12.288
81.4
-
40.7
40.7
48
20.8
1.3
19.5
6
-
-
-
-
4
4
.34
-
350
-
-
Max
-
-
-
-
-
750
45
45
-
-
-
-
12
-
-
6
6
6
6
1.0
-
-
-
25
Unit
ms
µs
µs
µs
MHz
ns
ps
ns
ns
kHz
µs
µs
µs
ns
ns
ns
ns
ns
ns
ns
µs
µs
ns
ns
ns
DS326PP4
7
 

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