CS4294 View Datasheet(PDF) - Cirrus Logic

Part Name

Description

View to exact match

CS4294

SoundFusion® Audio/Docking Codec ’97 (AMC’97)

Cirrus Logic 

CS4294

6.1.25 GPIO Pin Configuration (Index 4Ch)

D15 D14 D13 D12 D11 D10 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

0

0

0

0

0

0 res GC8 GC7 GC6 GC5 GC4 GC3 res res res

GC[9:0]

Default

GPIO Pin Configuration. When set defines the corresponding GPIO pin as an input

03FFh

After a cold reset, power up, or extended codec register reset (see Extended Codec ID (Index 3Ch))

all GPIO pins are configured as inputs.

6.1.26 GPIO Pin Polarity/Type Configuration (Index 4Eh)

D15 D14 D13 D12 D11 D10 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

1

1

1

1

1

1 res GP8 GP7 GP6 GP5 GP4 GP3 res res res

GP[9:0]

Default

GPIO Pin Configuration. The definition of GP[8:3] changes based on the pin defined as an input or an

output by GC[8:3] of GPIO Pin Configuration (Index 4Ch).

FFFFh

When the GPIO pin is defined as an input, its status is reported in the GPIO Pin Status (Index 54h)

register as well as Slot 12.

GCx

0

0

1

1

GPx

0

1

0

1

Function

Output

Output

Input

Input

CMOS drive

Open drain

Active Low

Active High (default)

Table 7. GPIO Input/Output Configuration

6.1.27 GPIO Pin Sticky (Index 50h)

D15 D14 D13 D12 D11 D10 D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

GS8 GS7 GS6 GS5 GS4 GS3

GS[8:3]

Default

GPIO Pin Sticky. If set, the GPIO pin input is latched.

0000h

If a GPIO is defined as “sticky” the input requires a transition of the GPIO input pin to set the corre-

sponding bit in Slot 12 and the GPIO Pin Status (Index 54h) register. When “sticky” is set the corre-

sponding bit in GPIO Pin Polarity/Type Configuration (Index 4Ah) register determines which edge

of the GPIO pin will set GI[x]. If GP[x] is set, a low to high transition sets the GI[x] bit. A high to

low transition sets GI[x] if GP[x] is clear. Once set, writing a 0 to GI[x] will clear the “sticky” input.

DS326PP4

27

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