CD4014 View Datasheet(PDF) - Intersil
Part Name
Description
View to exact match
CD4014 Datasheet PDF : 8 Pages
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Logic Diagram
CD40147BMS
0* 15
1* 11
2* 12
3* 13
4* 1
5* 2
6* 3
7* 4
8* 5
9* 10
FUNCTIONAL GATING
8
0
9
6
7
1
4
5
2
2
2
3
3
1
4
4
5
4
2
5
3
5
4
5
6
6
7
6
9
7
8
7
0
1
8
2
3
8
4
5
9
6
7
8
9
6
7
8
9
* ALL INPUTS ARE PROTECTED
BY CMOS PROTECTION
NETWORK
9A
7B
6C
14 D
VDD
VSS
FIGURE 1.
TRUTH TABLE (Negative Logic)
INPUTS
OUTPUTS
0
1
2
3
4
5
6
7
8
9
D
C
B
A
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
X
1
0
0
0
0
0
0
0
0
0
0
0
1
X
X
1
0
0
0
0
0
0
0
0
0
1
0
X
X
X
1
0
0
0
0
0
0
0
0
1
1
X
X
X
X
1
0
0
0
0
0
0
1
0
0
X
X
X
X
X
1
0
0
0
0
0
1
0
1
X
X
X
X
X
X
1
0
0
0
0
1
1
0
X
X
X
X
X
X
X
1
0
0
0
1
1
1
X
X
X
X
X
X
X
X
1
0
1
0
0
0
X
X
X
X
X
X
X
X
X
1
1
0
0
1
0 = High level 1 = Low level X = Don’t care
7-76
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