CAT24C023J-42TE13 View Datasheet(PDF) - Catalyst Semiconductor => Onsemi

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CAT24C023J-42TE13

Supervisory Circuits with I2C Serial CMOS E2PROM, Precision Reset Controller and Watchdog Timer

Catalyst Semiconductor => Onsemi 

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CAT24C163/083/043/023

FUNCTIONAL DESCRIPTION

The CAT24CXXX supports the I2C Bus data transmis-

sion protocol. This Inter-Integrated Circuit Bus protocol

defines any device that sends data to the bus to be a

transmitter and any device receiving data to be a re-

ceiver. The transfer is controlled by the Master device

which generates the serial clock and all START and

STOP conditions for bus access. The CAT24CXXX

operates as a Slave device. Both the Master device and

Slave device can operate as either transmitter or re-

ceiver, but the Master device controls which mode is

activated.

I2C BUS PROTOCOL

The features of the I2C bus protocol are defined as

follows:

(1) Data transfer may be initiated only when the bus is

not busy.

(2) During a data transfer, the data line must remain

stable whenever the clock line is high. Any changes in

the data line while the clock line is high will be interpreted

as a START or STOP condition.

START Condition

The START Condition precedes all commands to the

device, and is defined as a HIGH to LOW transition of

SDA when SCL is HIGH. The CAT24CXXX monitors the

SDA and SCL lines and will not respond until this

condition is met.

Figure 5. Acknowledge Timing

SCL FROM

1

MASTER

STOP Condition

A LOW to HIGH transition of SDA when SCL is HIGH

determines the STOP condition. All operations must end

with a STOP condition.

DEVICE ADDRESSING

The Master begins a transmission by sending a START

condition. The Master sends the address of the particu-

lar slave device it is requesting. The four most significant

bits of the 8-bit slave address are fixed as 1010.

The next three bits (Fig. 6) define memory addressing.

For the 24C023, the three bits are don't care. For the

24C043, the next two bits are don't care and the third bit

is the high order address bit. For the 24C083, the next

bit is don't care and the successive bits define the higher

order address bits. For the 24C163 the three bits define

higher order bits.

The last bit of the slave address specifies whether a

Read or Write operation is to be performed. When this

bit is set to 1, a Read operation is selected, and when set

to 0, a Write operation is selected.

After the Master sends a START condition and the slave

address byte, the CAT24CXXX monitors the bus and

responds with an acknowledge (on the SDA line) when

its address matches the transmitted slave address. The

CAT24CXXX then performs a Read or Write operation

depending on the state of the R/W bit.

8

9

DATA OUTPUT

FROM TRANSMITTER

DATA OUTPUT

FROM RECEIVER

START

Figure 6. Slave Address Bits

24C023 1 0 1 0 X X X R/W

ACKNOWLEDGE

24C083 1 0 1 0 X a9 a8 R/W

24C043 1 0 1 0 X X a8 R/W

24C163 1 0 1 0 a10 a9 a8 R/W

* 'X' Corresponds to Don't Care Bits (can be a zero or a one)

** a8, a9 and a10 correspond to the address of the memory array address word.

7

Doc. No. 25080-00 3/98 M-1

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