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CA3338D 데이터 시트보기 (PDF) - Intersil

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CA3338D CMOS Video Speed, 8-Bit, 50 MSPS, R2R D/A Converters Intersil
Intersil Intersil
CA3338D Datasheet PDF : 7 Pages
1 2 3 4 5 6 7
CA3338, CA3338A
STRAIGHT LINE
FROM “0” SCALE
TO FULL SCALE
VOLTAGE
= IDEAL TRANSFER CURVE
= ACTUAL TRANSFER CURVE
INTEGRAL LINEARITY
ERROR (SHOWN -)
delays. The VREF+ (and VREF- if bipolar) terminal should be
well bypassed as near the chip as possible.
“Glitch” energy is defined as a spurious voltage that occurs as
the output is changed from one voltage to another. In a binary
input converter, it is usually highest at the most significant bit
transition (7FHEX to 80HEX for an 8 bit device), and can be
measured by displaying the output as the input code alter-
nates around that point. The “glitch” energy is the area
between the actual output display and an ideal one LSB step
voltage (subtracting negative area from positive), at either the
positive or negative-going step. It is usually expressed in pV/s.
A
B
C A = IDEAL STEP SIZE (1/255 OF FULL
SCALE -“0” SCALE VOLTAGE)
B - A = +DIFFERENTIAL LINEARITY ERROR
C - A = -DIFFERENTIAL LINEARITY ERROR
0
00
INPUT CODE
FIGURE 4. D/A INTEGRAL AND DIFFERENTIAL LINEARITY
ERROR
Dynamic Characteristics
Keeping the full-scale range (VREF+ - VREF-) as high as
possible gives the best linearity and lowest “glitch” energy
(referred to 1V). This provides the best “P” and “N” channel
gate drives (hence saturation resistance) and propagation
The CA3338 uses a modified R2R ladder, where the 3 most
significant bits drive a bar graph decoder and 7 equally
weighted resistors. This makes the “glitch” energy at each 1/8
scale transition (1FHEX to 20HEX, 3FHEX to 40HEX, etc.)
essentially equal, and far less than the MSB transition would
otherwise display.
For the purpose of comparison to other converters, the output
should be resistively divided to 1V full scale. Figure 5 shows a
typical hook-up for checking “glitch” energy or settling time.
The settling time of the A/D is mainly a function of the output
resistance (approximately 160in parallel with the load resis-
tance) and the load plus internal chip capacitance. Both
“glitch” energy and settling time measurements require very
good circuit and probe grounding: a probe tip connector such
as Tektronix part number 131-0258-00 is recommended.
CLOCK
8 DATA BITS
+5V
15 LE
CA3338
1-7, 9
D0 - D7
16
VDD
+
14
COMP
8 VSS
12
VOUT
VREF+ 13
VREF- 11
VEE 10
+5V
+2.5V
-2.5V
R1
+
+
PROBE TIP
OR BNC
CONNECTOR
R2
REMOTE
VOUT
R3
DIGITAL
GROUND
FUNCTION
CONNECTOR
R1
R2
R3
Oscilloscope Display
Probe Tip
82
62
N/C
Match 93Cable
BNC
75
160
93
Match 75Cable
BNC
18
130
75
Match 50Cable
BNC
Short
75
50
NOTES:
2. VOUT(P-P) is approximate, and will vary as ROUT of D/A varies.
3. All drawn capacitors are 0.1µF multilayer ceramic/4.7µF tantalum.
4. Dashed connections are for unipolar operation. Solid connection are for bipolar operation.
FIGURE 5. CA3338 DYNAMIC TEST CIRCUIT
ANALOG
GROUND
VOUT (P-P)
1V
1V
1V
0 79V
10-16
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