FROM “0” SCALE
TO FULL SCALE
= IDEAL TRANSFER CURVE
= ACTUAL TRANSFER CURVE
ERROR (SHOWN -)
delays. The VREF+ (and VREF- if bipolar) terminal should be
well bypassed as near the chip as possible.
“Glitch” energy is deﬁned as a spurious voltage that occurs as
the output is changed from one voltage to another. In a binary
input converter, it is usually highest at the most signiﬁcant bit
transition (7FHEX to 80HEX for an 8 bit device), and can be
measured by displaying the output as the input code alter-
nates around that point. The “glitch” energy is the area
between the actual output display and an ideal one LSB step
voltage (subtracting negative area from positive), at either the
positive or negative-going step. It is usually expressed in pV/s.
C A = IDEAL STEP SIZE (1/255 OF FULL
SCALE -“0” SCALE VOLTAGE)
B - A = +DIFFERENTIAL LINEARITY ERROR
C - A = -DIFFERENTIAL LINEARITY ERROR
FIGURE 4. D/A INTEGRAL AND DIFFERENTIAL LINEARITY
Keeping the full-scale range (VREF+ - VREF-) as high as
possible gives the best linearity and lowest “glitch” energy
(referred to 1V). This provides the best “P” and “N” channel
gate drives (hence saturation resistance) and propagation
The CA3338 uses a modiﬁed R2R ladder, where the 3 most
signiﬁcant bits drive a bar graph decoder and 7 equally
weighted resistors. This makes the “glitch” energy at each 1/8
scale transition (1FHEX to 20HEX, 3FHEX to 40HEX, etc.)
essentially equal, and far less than the MSB transition would
For the purpose of comparison to other converters, the output
should be resistively divided to 1V full scale. Figure 5 shows a
typical hook-up for checking “glitch” energy or settling time.
The settling time of the A/D is mainly a function of the output
resistance (approximately 160Ω in parallel with the load resis-
tance) and the load plus internal chip capacitance. Both
“glitch” energy and settling time measurements require very
good circuit and probe grounding: a probe tip connector such
as Tektronix part number 131-0258-00 is recommended.
8 DATA BITS
D0 - D7
Match 93Ω Cable
Match 75Ω Cable
Match 50Ω Cable
2. VOUT(P-P) is approximate, and will vary as ROUT of D/A varies.
3. All drawn capacitors are 0.1µF multilayer ceramic/4.7µF tantalum.
4. Dashed connections are for unipolar operation. Solid connection are for bipolar operation.
FIGURE 5. CA3338 DYNAMIC TEST CIRCUIT