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CA3338D View Datasheet(PDF) - Intersil

Part NameDescriptionManufacturer
CA3338D CMOS Video Speed, 8-Bit, 50 MSPS, R2R D/A Converters Intersil
Intersil Intersil
CA3338D Datasheet PDF : 7 Pages
1 2 3 4 5 6 7
CA3338, CA3338A
Electrical Specifications TA = 25oC, VDD = 5V, VREF+ = 4.608V, VSS = VEE = VREF- = GND, LE Clocked at 20MHz, RL 1 M,
Unless Otherwise Specified (Continued)
PARAMETER
TEST CONDITIONS
MIN
REFERENCE VOLTAGE
VREF+ Range
VREF- Range
VREF+ Input Current
SUPPLY VOLTAGE
(+) Full Scale, Note 1
(-) Full Scale, Note 1
VREF+ = 6V, VDD = 6V
VREF- + 3
VEE
-
Static IDD or IEE
LE = Low, D0 - D7 = High
-
LE = Low, D0 - D7 = Low
-
Dynamic IDD or IEE
VOUT = 10MHz, 0V to 5V Square Wave
-
Dynamic IDD or IEE
VOUT = 10MHz, ±2.5V Square Wave
-
VDD Rejection
50kHz Sine Wave Applied
-
VEE Rejection
50kHz Sine Wave Applied
-
DIGITAL INPUTS D0 - D7, LE, COMP
High Level Input Voltage
Note 1
2
Low Level Input Voltage
Note 1
-
Leakage Current
-
Capacitance
-
TEMPERATURE COEFFICIENTS
Output Impedance
-
NOTE:
1. Parameter not tested. but guaranteed by design or characterization.
TYP
-
-
40
100
-
20
25
3
1
-
-
±1
5
200
MAX
VDD
VREF+ - 3
50
220
100
-
-
-
-
-
0.8
±5
-
-
UNITS
V
V
mA
µA
µA
mA
mA
mV/V
mV/V
V
V
µA
pF
ppm/oC
Pin Descriptions
PIN NAME
DESCRIPTION
1
D7 Most Significant Bit
2
D6
Input
3
D5
Data
4
D4
Bits
5
D3
(High = True)
6
D2
7
D1
8
VSS Digital Ground
9
D0 Least Significant Bit. Input Data Bit
10
VEE Analog Ground
11 VREF- Reference Voltage Negative Input
12
VOUT Analog Output
13 VREF+ Reference Voltage Positive Input
14 COMP Data Complement Control input. Active High
15
LE Latch Enable Input. Active Low
16
VDD Digital Power Supply, +5V
Digital Signal Path
The digital inputs (LE, COMP, and D0 - D7) are of TTL
compatible HCT High Speed CMOS design: the loading is
essentially capacitive and the logic threshold is typically
1.5V.
The 8 data bits, D0 (weighted 20) through D7 (weighted 27),
are applied to Exclusive OR gates (see Functional Diagram).
The COMP (data complement) control provides the second
input to the gates: if COMP is high, the data bits will be
inverted as they pass through.
The input data and the LE (latch enable) signals are next
applied to a level shifter. The inputs, operating between the
levels of VDD and VSS, are shifted to operate between VDD
and VEE. VEE optionally at ground or at a negative voltage,
will be discussed under bipolar operation. All further logic
elements except the output drivers operate from the VDD
and VEE supplies.
The upper 3 bits of data, D5 through D7, are input to a 3-to-7
line bar graph encoder. The encoder outputs and D0 through
D4 are applied to a feedthrough latch, which is controlled by
LE (latch enable).
10-14
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