TABLE 1. OUTPUT VOLTAGE vs INPUT CODE AND VREF
5.12V 5.00V 4.608V 2.56V 2.50V
0 -2.56V -2.50V
0.0200V 0.0195V 0.0180V 0.0200V 0.0195V
111111112=FFHEX 5.1000V 4.9805V 4.5900V 2.5400V 2.4805V
111111102=FEHEX 5.0800 4.9610 4.5720 2.5200 2.4610
2.3220 0.0200 0.0195
2.3040 0.0000 0.0000
2.2860 - 0.0200 -0.0195
000000012=01HEX 0.0200 0.0195 0.0180 -2.5400 -2.4805
000000002=00HEX 0.0000 0.0000 0.0000 -2.5600 -2.5000
The output of the CA3338 can be resistively divided to match a
doubly terminated 50Ω or 75Ω line, although peak-to-peak
swings of less than 1V may result. The output magnitude will
also vary with the converter’s output impedance. Figure 5
shows such an application. Note that because of the HCT input
structure, the CA3338 could be operated up to +7.5V VDD and
VREF+ supplies and still accept 0V to 5V CMOS input voltages.
If larger voltage swings or better accuracy is desired, a high
speed output buffer, such as the HA-5033, HA-2542, or
CA3450, can be employed. Figure 6 shows a typical
application, with the output capable of driving ±2V into
multiple 50Ω terminated lines.
Operating and Handling Considerations
All inputs and outputs of CMOS devices have a network for
electrostatic protection during handling. Recommended
handling practices for CMOS devices are described in
AN6525. “Guide to Better Handling and Operation of CMOS
During operation near the maximum supply voltage limit,
care should be taken to avoid or suppress power supply
turn-on and turn-off transients, power supply ripple, or
ground noise; any of these conditions must not cause the
absolute maximum ratings to be exceeded.
To prevent damage to the input protection circuit, input
signals should never be greater than VDD nor less than VSS.
Input currents must not exceed 20mA even when the power
supply is off.
A connection must be provided at every input terminal. All
unused input terminals must be connected to either VCC or
GND, whichever is appropriate.