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CA3338 View Datasheet(PDF) - Intersil

Part NameDescriptionManufacturer
CA3338 CMOS Video Speed, 8-Bit, 50 MSPS, R2R D/A Converters Intersil
Intersil Intersil
CA3338 Datasheet PDF : 10 Pages
1 2 3 4 5 6 7 8 9 10
CA3338, CA3338A
Absolute Maximum Ratings
DC Supply-Voltage Range . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +8V
(VDD - VSS or VDD - VEE, Whichever is Greater)
Input Voltage Range
Digital Inputs (LE, COMP D0 - D7). . . . VSS - 0.5V to VDD + 0.5V
Analog Pins (VREF+, VREF-, VOUT) . . . . VDD - 8V to VDD + 0.5V
DC Input Current
Digital Inputs (LE, COMP, D0 - D7) . . . . . . . . . . . . . . . . . . ±20mA
Recommended Supply Voltage Range . . . . . . . . . . . . . 4.5V to 7.5V
Thermal Information
Thermal Resistance (Typical, Note 1)
θJA (oC/W) θJC (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . .
90
N/A
SOIC Package . . . . . . . . . . . . . . . . . . . 100
N/A
Maximum Junction Temperature
Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150oC
Maximum
Maximum
Storage Temperature Range,
Lead Temperature (Soldering
TSTG
10s) .
.
.
.
.
.
.
.
.
-65oC to 150oC
. . . . . . . .300oC
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range (TA)
Plastic Package, E suffix,
M
suffix
.
.
.
.
.
.
.
.
.
.
.
.
.
.
-40oC
to
85oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications TA = 25oC, VDD = 5V, VREF+ = 4.608V, VSS = VEE = VREF- = GND, LE Clocked at 20MHz, RL 1 M,
Unless Otherwise Specified
PARAMETER
TEST CONDITIONS
MIN
ACCURACY
Resolution
8
Integral Linearity Error
See Figure 4
CA3338
-
CA3338A
-
Differential Linearity Error
See Figure 4
CA3338
-
CA3338A
-
Gain Error
CA3338
Input Code = FFHEX, See Figure 3
-
CA3338A
-
Offset Error
Input Code = 00HEX; See Figure 3
-
DIGITAL INPUT TIMING
Update Rate
To Maintain 1/2 LSB Settling
DC
Update Rate
VREF- = VEE = -2.5V, VREF+ = +2.5V
DC
Set Up Time tSU1
For Low Glitch
-
Set Up Time tSU2
For Data Store
-
Hold Time tH
For Data Store
-
Latch Pulse Width tW
For Data Store
-
Latch Pulse Width tW
VREF- = VEE = -2.5V, VREF+ = +2.5V
-
OUTPUT PARAMETERS RL Adjusted for 1VP-P Output
Output Delay tD1
From LE Edge
-
Output Delay tD2
From Data Changing
-
Rise Time tr
10% to 90% of Output
-
Settling Time tS
10% to Settling to 1/2 LSB
-
Output Impedance
VREF+ = 6V, VDD = 6V
120
Glitch Area
-
Glitch Area
VREF- = VEE = -2.5V,VREF+ = +2.5V
-
TYP
MAX
UNITS
-
-
Bits
-
±1
LSB
-
±0.75
LSB
-
±0.75
LSB
-
±0.5
LSB
-
±0.75
LSB
-
±0.5
LSB
-
±0.25
LSB
50
-
MHz
20
-
MHz
-2
-
ns
8
-
ns
5
-
ns
5
-
ns
25
-
ns
25
-
ns
22
-
ns
4
-
ns
20
-
ns
160
200
150
-
pV/s
250
-
pV/s
3
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