CA3306, CA3306A, CA3306C
Application Circuits (Continued)
CLOCK
INPUT
V+
0.1µF
B6
B5
OF
B4
RC
VSS
CA3306
VZ
B3
CE2
B2
CE1
B1
CLK
VSS
VDD
PH
VIN
VREF+ VREF-
0.1µF
0.2µF
V+
10µF
(MSB)
B6
B5
B4
DATA
OUTPUT
B3
B2
(LSB)
B1
ADJUST POT
TO 1/2 VZ
V+
V+
0.1µF
B6
B5
OF
B4
CA3306
VSS
RC
VZ
CE2
CE1
CLK
B3
B2
B1
VDD
PH
VIN
VREF -
VREF +
0.1µF
0.2µF
10µF
NOTE:
VDD MUST BE ≥ VZ FOR CIRCUIT TO WORK
WITH VZ CONNECTED TO VREF+
SIGNAL
INPUT
FIGURE 18. TYPICAL CA3306 6-BIT RESOLUTION CONFIGURATION WITH DOUBLE SAMPLING RATE CAPABILITY
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