C8051F320/1 View Datasheet(PDF) - Silicon Laboratories
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C8051F320/1 Datasheet PDF : 250 Pages
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C8051F320/1
4. Pinout and Package Definitions
Table 4.1. Pin Definitions for the C8051F320/1
Name
Pin Numbers
Type Description
‘F320 ‘F321
Power In 2.7-3.6 V Power Supply Voltage Input.
VDD
GND
/RST/
6
6
Power
Out 3.3 V Voltage Regulator Output. See Section 8.
3
3
Ground.
D I/O Device Reset. Open-drain output of internal POR or VDD
monitor. An external source can initiate a system reset by
9
9
driving this pin low for at least 15 µs. See Section 10.
C2CK
P3.0/
C2D
REGIN
VBUS
D+
D-
P0.0
P0.1
P0.2/
XTAL1
P0.3/
D I/O Clock signal for the C2 Debug Interface.
D I/O Port 3.0. See Section 14 for a complete description.
10 10
D I/O Bi-directional data signal for the C2 Debug Interface.
7
7
Power In 5 V Regulator Input. This pin is the input to the on-chip volt-
age regulator.
VBUS Sense Input. This pin should be connected to the
8
8
D In VBUS signal of a USB network. A 5 V signal on this pin indi-
cates a USB network connection.
4
4
D I/O USB D+.
5
5
D I/O USB D–.
2
2
D I/O Port 0.0. See Section 14 for a complete description of Port 0.
1
1
D I/O Port 0.1.
D I/O Port 0.2.
32 28
External Clock Input. This pin is the external oscillator return
A In for a crystal or resonator. See Section 13.
D I/O Port 0.3.
XTAL2
P0.4
P0.5
P0.6/
CNVSTR
P0.7/
VREF
P1.0
31
27
External Clock Output. This pin is the excitation driver for an
A I/O or external crystal or resonator, or an external clock input for
D In CMOS, capacitor, or RC oscillator configurations. See Sec-
tion 13.
30 26 D I/O Port 0.4.
29 25 D I/O Port 0.5.
Port 0.6.
28 24
ADC0 External Convert Start Input. See Section 5.
D I/O Port 0.7.
27 23
A I/O External VREF input or output. See Section 6.
26
22
D I/O or
A In
Port 1.0. See Section 14 for a complete description of Port 1.
30
Rev. 1.4
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