C8051F320 View Datasheet(PDF) - Unspecified

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C8051F320

Full Speed USB, 16k ISP FLASH MCU Family

Unspecified 

C8051F320/1

1.10. Comparators

C8051F320/1 devices include two on-chip voltage comparators that are enabled/disabled and configured via user

software. Port I/O pins may be configured as comparator inputs via a selection mux. Two comparator outputs may be

routed to a Port pin if desired: a latched output and/or an unlatched (asynchronous) output. Comparator response time

is programmable, allowing the user to select between high-speed and low-power modes. Positive and negative hyster-

esis are also configurable.

Comparator interrupts may be generated on rising, falling, or both edges. When in IDLE mode, these interrupts may

be used as a “wake-up” source. Comparator0 may also be configured as a reset source. Figure 1.11 shows the

Comparator0 block diagram.

Figure 1.11. Comparator0 Block Diagram

CMX0N1

CMX0N0

CMX0P1

CMX0P0

P1.0

P1.4

P2.0

P2.4

CP0EN

CP0OUT

CP0RIF

CP0FIF

CP0HYP1

CP0HYP0

CP0HYN1

CP0HYN0

CP0 +

P1.1

P1.5

CP0 -

P2.1

P2.5

VDD

CP0

Interrupt

CP0

Rising-edge

CP0

Falling-edge

+

-

GND

D SET Q

Q

CLR

D SET Q

Q

CLR

(SYNCHRONIZER)

Reset

Decision

Tree

Interrupt

Logic

CP0RIE

CP0FIE

CP0

Crossbar

CP0A

Note: P2.4 and P2.5 available

only on C8051F320

CP0RIE

CP0FIE

CP0MD1

CP0MD0

28

Rev. 1.1

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