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YGV627 View Datasheet(PDF) - Yamaha Corporation

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YGV627 Datasheet PDF : 16 Pages
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YGV627
q FSC ( O )
This pin outputs sub-carrier clock for video encoder.
This pin can output a clock inputted to DTCKIN pin divided by 1, 2, 4 or 8 which may be selected in accordance
with the register setting. Inputting a clock of 14.318 MHz into DTCKIN pin provides sub-carrier clock of 3.58 MHz
when divided by 4.
q DOTCLK ( O )
Output signal of display data (analog R, G, B, DV17DV0, YS, AT) is outputted synchronizing with DOTCLK.
q DVOUT ( I: PULL UP )
This pin selects input/output of external video data terminal.
The external video terminal becomes output when low level is inputted to this pin, or input when high level is
inputted to this pin. The input/output of the external video data terminal can be changed with internal register
EXIO(R#05). In such case, input high level to DVOUT or keep it open.
q DV170 ( I/O: PULL UP )
These are input/output pins for digital external video data.
These pins become input when high level is inputted to DVOUT and EXIO(R#05) =“0” is set, or becomes output
when low level is inputted to DVOUT pin or EXIO(R#05) =“1” is set.
For the external video data, a format with 6 bits for digital RGB individually, or a format with 6 bits for CrYCb
individually can be selected.
The format of the input / output data is as shown below.
DV17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R(Cr)50(I/O)
G(Y)50(I/O)
B(Cb)50(I/O)
q YS ( O )
When performing superimposition, this pin outputs a signal that controls switching with external signal.
When displaying bitmap plane, this pin outputs inversion signal for YSN bits that can be set by dot.
In the border displaying period or blank period, this pin outputs inversion signal of border YS data.
q AT ( O )
This pin outputs 1 bit attribute data that can be set by display dot. When ATE(R#05) signal of internal register is set
to “0”, the value set in the ATD bit of register is outputted regardless the display data.
When “1” is set for ATE signal, B0 (LSB of Blue) that is inputted to DAC for blue is outputted from AT pin.
At this time, the same data of MSB is inputted to LSB of DAC for blue.
During the blank period, B0 of border is outputted when ATE signal is set to “1”. When the signal is set to “1”, the
value set to ATD bit is outputted.
This signal can be used, for example, for specifying semi-transparency (YM) when externally mixing display data.
q VSIN ( I: PULL UP )
This signal resets the vertical timing of CRT controller block of YGV627. When this input signal is sampled with
period equal to the pulse width of horizontal sync signal, and low level is detected three times consecutively, the
internal V counter is set at the first HTL timing (horizontal sync signal start timing) immediately after the moment. In
interlace mode, field identification is performed at the resetting of vertical timing by inputting composite sync signal
of external video through this pin. This feature allows the superimposition synchronizing with frame period easily. If
this signal is inputted during the display period, the display data of the next one field is not guaranteed. This pin can
be kept open if this function is not used. The function of this pin is the same as that of VRESET pin of YGV617B.
Horizontal sync pulse width
Sampling Clock
VSIN
HTL Timing
V-Counter
?
Counter set
9
 

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