BT8110 View Datasheet(PDF) - Unspecified

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BT8110

High-Capacity ADPCM Processor

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Bt8110/8110B

High-Capacity ADPCM Processor

2.0 Functional Description

2.2 Modes of Operation

Bits e1 and e0 of the decoder input are used only for embedded coding

operation where they specify the number of bits in the applied decoder input.

Unused decoder input bits must be set to 0.

Table 2-2. Parallel Signal Input Bus

Input Bus

Encoder In

Decoder In

PSIG[7]

PSIG[6]

PSIG[5]

PSIG[4]

PSIG[3]

PSIG[2]

PSIG[1]

PSIG[0]

Sign Bit

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

Bit 8

I1

I2

I3

I4

I5

e1 - 0 for 3 or 2 bits, 1 for 5 or 4 bits

e0 - 0 for 4 or 2 bits, 1 for 5 or 3 bits

0

If PSIGEN is low, the only PSIG[7:0] bus inputs used are PSIG[2] and

PSIG[1]. These are used as inputs for embedded decoding. The other PSIG inputs

should be held at a logic low level; these inputs have internal pull-down circuits.

Driving these inputs when only serial inputs are enabled will induce test modes in

the part that will interfere with proper operation.

SERIAL_OUT represents the timing on the serial ADPCM signals as shown

in Figure 2-3. The ADPCM output is from the channel whose PCM signal was

applied 56 clock cycles previously. The PCM output is from the channel whose

ADPCM input was applied 88 clock cycles previously. Unused ADPCM output

bits are set to 0.

D[7:0] outputs are the 8 output bits of the ROM and are used for the parallel

signal outputs at the indicated time. Table 2-3 gives the arrangement of the output

bits on the bus.

NOTE: On Bt8110B only, when internal ROM is used, the bidirect outputs D[7:0]

will contain the PCM/ADPCM output values, MSB on D[7]. Each output

word will be latched simultaneously with the falling edge of the PCM and

ADPCM strobe signals. In interleaved mode, the output timing will appear

as shown by signal D[7:0] Int in Figure 2-3.

The delay of the parallel outputs can be observed in Figure 2-3. When parallel

inputs are used, the ADPCM output for encoder operations is available 48 clock

cycles after the input is applied. The PCM output of decoder operations is

available 80 clock cycles after the input is applied.

When the channel control is set for transparent operation, the 8-bit output

field is exactly the same as the 8-bit input field for either parallel or serial inputs.

The delay is kept the same as for coding operations.

100060C

Conexant

2-7

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