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BT8110

High-Capacity ADPCM Processor

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Bt8110/8110B

High-Capacity ADPCM Processor

1.0 Product Description

1.2 Pin Descriptions

Table 1-4. Bt8110/8110B Hardware Signal Definitions (2 of 2)

Pin Label

Signal Name

I/O

Definition

A[13:0]

ROM Address Bus

CTRL[1,0]

Control Inputs

I/O On the Bt8110, these signals are ouputs driving the address lines

on the external lookup table ROM. On the Bt8110B, A[7:0] are

inputs when internal lookup table ROM is used. A[13:8] must be

left open when using the Bt8110B with internal lookup table ROM

enabled.

A[7:0] may be left open or held low for normal operation when

using Bt8110B with internal lookup table ROM enabled.

When using the Bt8110B with internal lookup table ROM

enabled, A[0] and A[3] have the following functions:

• A[0] Disable G.726 TR predictor reset. This function forces the

output TD of block TONE to a value of 0.

• A[3] Disable even-bit inversion in A-law. This function disables

even-bit inversion per G.711.

Signal A[0] will be sampled at the same input times as the

code select inputs, and so “disable predict or reset” can be

controlled on a channel-by-channel bases. A[3] is not timed

and so it affects every channel.

• A[2:0], A[5:4] are used to allow the Bt8110B to be compatible

with pre-Bt8110 designs.

• A[7:6] are factory test pins on the Bt8110B that must always

be open or held at logic low level.

I On the Bt8110B two new control inputs are provided in place of

Vcc and GND. CTRL[1] (pin 39) is Vcc in the Bt8110, and CTRL[0]

is GND in Bt8110.

The modes that these new control inputs implement are:

CTRL[1]

low

low

high

high

CTRL[0]

Mode

low Internal ROM only, interleaved,

encode only & decode only modes

high Internal ROM only, direct framer

interface. This option provides a

hardware-mode direct framer

interface.

low Bt8110–compatible mode, external

ROM required

high Not used (production test only)

VCC

Supply

GND

Ground

In Bt8110-compatible mode, existing ROMS will work.

I Seven pins are provided for supply voltage on the Bt8110. Six pins

are provided on the Bt8110B.

I Nine pins are provided for ground on the Bt8110. Eight pins are

provided on the Bt8110B.

SE

SE Parameter

O The serial output pin for the SE parameter. Used only for factory

test purposes and should be left unconnected.

TDP

TDP Parameter

O The serial output pin for the TDP parameter. Used only for factory

test purposes and should be left unconnected.

Y

Y Parameter

O The serial output pin for the Y parameter. Used only for factory test

purposes and should be left unconnected.

NOTE(S):

(1) All inputs are active high except WR* which adapts to the type of microprocessor being used. See Section 2.1.2.

100060C

Conexant

1-11

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